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1. SystemVerilogCoEmulation_POC SystemVerilogCoEmulation_POC Public

   Proof of concept for co-emulation using SystemVerilog. Eliminating need for scripting langs and writing different testbenches for both simulation and hardware tests.

   C 2

2. verilator/verilator verilator/verilator Public

   Verilator open-source SystemVerilog simulator and lint system

   C++ 2.6k 624

3. ml_in_chisel ml_in_chisel Public

   Inspired by Tsodings ventures in ML with C, this is an FPGA hardware implementation of the simple example seen at the start of episode 1.

   Scala

4. MaCH MaCH Public

   MaCH - Matrices in CHISEL

   Scala

5. cryptoProcessor cryptoProcessor Public

   VHDL