Wish that Great job to be done here ✨
- GEM5新增ROB feature
- 尽快上线
REmind
- ISP- CGRA新型架构及FULL-STACK工具--- DATE 9月18日/FPGA 10月7日
- 通用CGRA-ISA及后端解耦思想:软硬件敏捷开发 --- DAC 11月/12月
Wish that Great job to be done here ✨
REmind
THU-VLSI digital circuit-lab assignment. Group collaboration with yuanzhao, yunlonghe, siyuanjiao @2021 winter.
SourcePawn 2
THU-Integreted Circuit Design and Methodology-lab assignment @2021 autumn
Verilog 2
THU Micro-Processor-Design lab assignment @2022 summer
Verilog 2
THU VLSI-HLS lab assignment. Group collaboration with kexiangdeng, jiaweiliu, yuxuanli @2022 summer.