Merge pull request pyocd#577 from flit/feature/core_check

Check that at least one core was found

docs/configuration.md

@@ -66,6 +66,8 @@ frequency: 8000000 # Set 8 MHz SWD default for all probes
 
 ## Options list
 
+- `allow_no_cores`: (bool) Prevents raising an error if no core were found after CoreSight discovery. Default is False.
+
 - `auto_unlock`: (bool) If the target is locked, it will by default be automatically mass erased in
     order to gain debug access. Set this option to False to disable auto unlock. Default is True.
 

pyocd/core/coresight_target.py

@@ -16,6 +16,7 @@
 
 from .target import Target
 from .memory_map import MemoryType
+from . import exceptions
 from ..flash.loader import FlashEraser
 from ..coresight import (dap, cortex_m, rom_table)
 from ..debug.svd import (SVDFile, SVDLoader)
@@ -134,6 +135,7 @@ def create_init_sequence(self):
             ('init_ap_roms',        self.dp.init_ap_roms),
             ('create_cores',        self.create_cores),
             ('create_components',   self.create_components),
+            ('check_for_cores',     self.check_for_cores),
             ('notify',              lambda : self.notify(Notification(event=Target.EVENT_POST_CONNECT, source=self)))
             )
 
@@ -212,6 +214,15 @@ def _apply_to_all_components(self, action, filter=None):
         for ap in [x for x in self.dp.aps.values() if x.has_rom_table]:
             ap.rom_table.for_each(action, filter)
 
+    def check_for_cores(self):
+        """! @brief Init task: verify that at least one core was discovered."""
+        if not len(self.cores):
+            # Allow the user to override the exception to enable uses like chip bringup.
+            if self.session.options.get('allow_no_cores', False):
+                logging.error("No cores were discovered!")
+            else:
+                raise exceptions.Error("No cores were discovered!")
+
     def disconnect(self, resume=True):
         self.notify(Notification(event=Target.EVENT_PRE_DISCONNECT, source=self))
         self.call_delegate('will_disconnect', target=self, resume=resume)

pyocd/core/options.py

@@ -20,6 +20,7 @@
 
 OPTIONS_INFO = {
     # Common options
+    'allow_no_cores': OptionInfo('allow_no_cores', bool, "Prevents raising an error if no core were found after CoreSight discovery."),
     'auto_unlock': OptionInfo('auto_unlock', bool, "Whether to unlock secured target by erasing."),
     'chip_erase': OptionInfo('chip_erase', str, "Whether to perform a chip erase or sector erases when programming flash."),
     'config_file': OptionInfo('config_file', str, "Path to custom config file."),

pyocd/coresight/cortex_m.py

@@ -549,9 +549,9 @@ def _read_core_type(self):
             self._supports_vectreset = True
 
         if self.core_type in CORE_TYPE_NAME:
-            logging.info("CPU core is %s r%dp%d", CORE_TYPE_NAME[self.core_type], self.cpu_revision, self.cpu_patch)
+            logging.info("CPU core #%d is %s r%dp%d", self.core_number, CORE_TYPE_NAME[self.core_type], self.cpu_revision, self.cpu_patch)
         else:
-            logging.info("CPU core is unknown")
+            logging.warning("CPU core #%d type is unrecognized", self.core_number)
 
     ## @brief Determine if a core has an FPU.
     #

pyocd/tools/pyocd.py

@@ -544,7 +544,10 @@ def run(self):
                         if self.target.is_locked():
                             status = "locked"
                         else:
-                            status = CORE_STATUS_DESC[self.target.get_state()]
+                            try:
+                                status = CORE_STATUS_DESC[self.target.get_state()]
+                            except KeyError:
+                                status = "<no core>"
 
                         # Say what we're connected to.
                         print("Connected to %s [%s]: %s" % (self.target.part_number,