Berkeley's Spatial Array Generator

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

Hardware Accelerator for Self Attention Layer in Bluespec - for Shakti C Class

The aim of this project is to create CNN for CIFAR10 database, for which an accelerator will be created on FPGA. There is implementation using Keras library and implementation without using Keras.

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

Generator of verilog description for FPGA MobileNet implementation

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

搭建卷积神经网络并利用FPGA加速实现交通标志识别

FPGA project