build/configs/rtl8720e/scripts: Correct PSRAM Heap size and layout

Current LD has removed PSRAM layout and assigned incorrect PSRAM HEAP start address Add PSRAM layout into LD and correct PSRAM Heap start address.
Hyperion-Consulting · Nov 30, 2022 · c1ea05d · c1ea05d
1 parent 24d2156
commit c1ea05d
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Showing 2 changed files with 20 additions and 3 deletions.
diff --git a/build/configs/rtl8720e/scripts/rlx8720e_img2_ns.ld b/build/configs/rtl8720e/scripts/rlx8720e_img2_ns.ld
@@ -83,7 +83,7 @@ MEMORY
 	/* IMG2 RAM */
 	KM4_BD_RAM (rwx) :                      ORIGIN = 0x20012020, LENGTH = 0x20040000 - 0x20012020	/* KM4 BD RAM: 184k */
 	KR4_BD_RAM (rwx) :                      ORIGIN = 0x20040060, LENGTH = 0x2007A000 - 0x20040060	/* KR4 BD RAM: 232k */
-	KM4_HEAP_EXT (rwx) :                    ORIGIN = 0x2007A000, LENGTH = 0x200B0000 - 0x2007A000	/* KM4 HEAP EXT: 280k(8720EA) */
+	KM4_HEAP_EXT (rwx) :                    ORIGIN = 0x2007A000, LENGTH = 0x200B0000 - 0x2007A000	/* KM4 HEAP EXT: 216k(8720EA) */
 	KM4_BD_RAM_TZ_NSC (rwx) :               ORIGIN = 0x200B0020, LENGTH = 0x200B1000 - 0x200B0020	/* KM4 BD RAM NSC: 4k */
 	KM4_BD_RAM_TZ_ENTRY (rwx) :             ORIGIN = 0x200B1000, LENGTH = 0x200B3000 - 0x200B1000	/* KM4 BD RAM ENTRY: 8k */
 	KM4_BD_RAM_TZ_S (rwx) :                 ORIGIN = 0x300B3020, LENGTH = 0x300C0000 - 0x300B3020	/* KM4 BD RAM S: 52k */
@@ -299,11 +299,28 @@ SECTIONS
 
 	.bdram_heap.start (NOLOAD):
 	{
+		/* For TizenRT to locate idle thread stack */
 		_sbss = ABSOLUTE(.);
 		__bdram_heap_buffer_start__ = .;
+		/* For TizenRT to locate idle thread stack */
 		_ebss = ABSOLUTE(.);
 	} > KM4_BD_RAM
 
+	/* psram part */
+	.psram_image2.text.data :
+	{
+		*(.timesensitive.data*)
+		*(.data*)
+
+		/*cache line size aligned in order to avoid MMU remap err*/
+		. = ALIGN(32);
+	} > KM4_BD_PSRAM
+
+	.psram_heap.start (NOLOAD):
+	{
+		__psram_heap_buffer_start__ = .;
+	} > KM4_BD_PSRAM
+
 	.bluetooth_trace.text :
 	{
 		__btrace_start__ = .;

diff --git a/os/board/rtl8720e/src/component/soc/amebalite/fwlib/ram_km4/ameba_app_start.c b/os/board/rtl8720e/src/component/soc/amebalite/fwlib/ram_km4/ameba_app_start.c
@@ -43,15 +43,15 @@ extern u32 GlobalDebugEnable;
 #ifdef CONFIG_PLATFORM_TIZENRT_OS
 extern unsigned int __StackStart;
 extern unsigned int __StackLimit;
-extern unsigned int _ebss;
+extern uint8_t __psram_heap_buffer_start__[];
 extern unsigned int __PsramStackLimit;
 void NS_ENTRY BOOT_IMG3(void);
 void app_init_psram(void);
 
 #define IDLE_STACK ((uintptr_t)&__StackStart+CONFIG_IDLETHREAD_STACKSIZE-4)
 #define HEAP_BASE  ((uintptr_t)&__StackStart+CONFIG_IDLETHREAD_STACKSIZE)
 #define HEAP_LIMIT ((uintptr_t)&__StackLimit)
-#define PSRAM_HEAP_BASE ((uintptr_t)&_ebss)
+#define PSRAM_HEAP_BASE ((uintptr_t)&__psram_heap_buffer_start__)
 #define PSRAM_HEAP_LIMIT ((uintptr_t)&__PsramStackLimit)
 
 void os_heap_init(void){