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rocket-ap-rtl Public
Rocket chip with an Asocciative Processor attached in RTL for FPGA
Verilog UpdatedOct 28, 2024 -
rocket-ap-fw Public
Firmware to control the Associative Processor integrated with Rocket Chip
C UpdatedOct 23, 2024 -
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riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedJan 5, 2023 -
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inf-0536 Public
inf-0536: Princípios de operação e Projeto de Sistemas IoT
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freedom Public
Forked from sifive/freedomSource files for SiFive's Freedom platforms
Scala Apache License 2.0 UpdatedJul 17, 2021 -
FreeRTOS-RISCV Public
Forked from illustris/FreeRTOS-RISCVA port of FreeRTOS for the RISC-V ISA
C UpdatedJul 14, 2021 -
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fpnew Public
Forked from openhwgroup/cvfpuParametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
SystemVerilog Other UpdatedApr 19, 2021 -
riscv-gnu-toolchain Public
Forked from riscv-collab/riscv-gnu-toolchainGNU toolchain for RISC-V, including GCC
C Other UpdatedApr 7, 2021 -
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datasharing Public
Forked from jtleek/datasharingThe Leek group guide to data sharing
UpdatedSep 2, 2020 -
riscv-tools Public
Forked from riscv-software-src/riscv-toolsRISC-V Tools (ISA Simulator and Tests)
Shell UpdatedAug 21, 2020 -
riscv-vp Public
Forked from agra-uni-bremen/riscv-vpRISC-V Virtual Prototype
C++ MIT License UpdatedJul 23, 2020 -
rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedFeb 25, 2020 -
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FPGA-Design-Flow-using-Vivado Public
Forked from xupgit/FPGA-Design-Flow-using-VivadoThis course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
HTML UpdatedOct 15, 2019 -
fpu Public
Forked from dawsonjon/fpusynthesiseable ieee 754 floating point library in verilog
Verilog MIT License UpdatedOct 14, 2019 -
Verilog-FIR Public
Forked from Grootzz/Verilog-FIRFIR implemention with Verilog
Verilog UpdatedMay 18, 2019 -
fibonacci Public
Forked from robinmessage/fibonacciA simple C++ fibonacci heap implementation
C++ UpdatedMay 14, 2019 -
ReonV Public
Forked from lcbcFoo/ReonVReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
VHDL GNU General Public License v3.0 UpdatedOct 7, 2018 -
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