Skip to content

Commit

Permalink
Merge Pull Request sstsimulator#1769 from nmhamster/sst-elements/vana…
Browse files Browse the repository at this point in the history 
…dis-riscv

Automatically Merged using SST Pull Request AutoTester
PR Title: b'Additional RISCV Instruction Support'
PR Author: nmhamster
  • Loading branch information
@sst-autotester
sst-autotester authored Dec 3, 2021
2 parents b49f5c1 + 1737ee2 commit 9494c59
Showing 1 changed file with 50 additions and 13 deletions.
63 changes: 50 additions & 13 deletions src/sst/elements/vanadis/decoder/vriscv64decoder.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -789,7 +789,7 @@ class VanadisRISCV64Decoder : public VanadisDecoder
switch ( func_code6 ) {
case 0x0:
{
output->verbose(CALL_INFO, 16, 0, "--------> SRLI %" PRIu16 " <- %" PRIu16 " << %" PRIu32 "\n",
output->verbose(CALL_INFO, 16, 0, "--------> SRLI %" PRIu16 " <- %" PRIu16 " >> %" PRIu32 "\n",
rd, rs1, shift_by);
bundle->addInstruction(
new VanadisShiftRightLogicalImmInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT64>(
Expand All @@ -798,7 +798,7 @@ class VanadisRISCV64Decoder : public VanadisDecoder
} break;
case 0x40000000:
{
output->verbose(CALL_INFO, 16, 0, "--------> SRAI %" PRIu16 " <- %" PRIu16 " << %" PRIu32 "\n",
output->verbose(CALL_INFO, 16, 0, "--------> SRAI %" PRIu16 " <- %" PRIu16 " >> %" PRIu32 "\n",
rd, rs1, shift_by);
bundle->addInstruction(
new VanadisShiftRightArithmeticImmInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT64>(
Expand Down Expand Up @@ -963,6 +963,16 @@ class VanadisRISCV64Decoder : public VanadisDecoder
ins_address, hw_thr, options, rd, rs1, rs2));
decode_fault = false;
} break;
case 32:
{
// SRA
output->verbose(CALL_INFO, 16, 0, "-------> SRA %" PRIu16 " <- %" PRIu16 " >> %" PRIu16 "\n",
rd, rs1, rs2);
bundle->addInstruction(
new VanadisShiftRightArithmeticInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT64>(
ins_address, hw_thr, options, rd, rs1, rs2));
decode_fault = false;
} break;
};
} break;
case 6:
Expand Down Expand Up @@ -1050,8 +1060,8 @@ class VanadisRISCV64Decoder : public VanadisDecoder
{
// RS2 acts as an immediate
// SLLIW (32bit result generated)
output->verbose(CALL_INFO, 16, 0, "-------> SLLIW %" PRIu16 " <- %" PRIu16 " << %" PRIu16 "\n",
rd, rs1, rs2);
output->verbose(CALL_INFO, 16, 0, "-------> SLLIW %" PRIu16 " <- %" PRIu16 " << %" PRIu16 " (0x%lx)\n",
rd, rs1, rs2, rs2);
bundle->addInstruction(new VanadisShiftLeftLogicalImmInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT32>(
ins_address, hw_thr, options, rd, rs1, rs2));
decode_fault = false;
Expand All @@ -1065,12 +1075,23 @@ class VanadisRISCV64Decoder : public VanadisDecoder
{
// RS2 acts as an immediate
// SRLIW (32bit result generated)
output->verbose(CALL_INFO, 16, 0, "-------> SRLIW %" PRIu16 " <- %" PRIu16 " << %" PRIu16 "\n",
rd, rs1, rs2);
output->verbose(CALL_INFO, 16, 0, "-------> SRLIW %" PRIu16 " <- %" PRIu16 " << %" PRIu16 " (0x%lx)\n",
rd, rs1, rs2, rs2);
bundle->addInstruction(new VanadisShiftRightLogicalImmInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT32>(
ins_address, hw_thr, options, rd, rs1, rs2));
decode_fault = false;

} break;
case 32:
{
// RS2 acts as an immediate
// SRAIW
output->verbose(CALL_INFO, 16, 0, "-------> SRAIW %" PRIu16 " <- %" PRIu16 " << %" PRIu16 " (0xlx)\n",
rd, rs1, rs2, rs2);
bundle->addInstruction(
new VanadisShiftRightArithmeticImmInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT32>(
ins_address, hw_thr, options, rd, rs1, rs2));
decode_fault = false;
} break;
}
} break;
Expand Down Expand Up @@ -1212,6 +1233,7 @@ class VanadisRISCV64Decoder : public VanadisDecoder
bundle->addInstruction(
new VanadisMultiplyInstruction<VanadisRegisterFormat::VANADIS_FORMAT_INT32>(
ins_address, hw_thr, options, rd, rs1, rs2));
decode_fault = false;
} break;
case 0x20:
{
Expand Down Expand Up @@ -1423,6 +1445,21 @@ class VanadisRISCV64Decoder : public VanadisDecoder
case 0x2000:
{
// FLD
uint16_t rvc_rd = expand_rvc_int_register(extract_rs2_rvc(ins));
uint16_t rvc_rs1 = expand_rvc_int_register(extract_rs1_rvc(ins));

uint32_t imm_53 = (ins & 0x1C00) >> 7;
uint32_t imm_76 = (ins & 0x60) << 1;

uint32_t imm = (imm_53 | imm_76);

output->verbose(CALL_INFO, 16, 0, "-------> RVC FLD %" PRIu16 " <- memory[ %" PRIu16 " + %" PRIu32 " ]\n",
rvc_rd, rvc_rs1, imm);

bundle->addInstruction(new VanadisLoadInstruction(
ins_address, hw_thr, options, rvc_rs1, imm, rvc_rd, 8, true, MEM_TRANSACTION_NONE,
LOAD_FP_REGISTER));
decode_fault = false;
} break;
case 0x4000:
{
Expand Down Expand Up @@ -2079,13 +2116,13 @@ class VanadisRISCV64Decoder : public VanadisDecoder
}


if(fatal_decode_fault) {
output->fatal(CALL_INFO, 16, 0, "[decode] -> decode fault detected at 0x%llx / thr: %" PRIu32 ", set to fatal on detect\n", ins_address,
hw_thr);
}
if(decode_fault) {
bundle->addInstruction(new VanadisInstructionDecodeFault(ins_address, hw_thr, options));
}
if(decode_fault) {
if(fatal_decode_fault) {
output->fatal(CALL_INFO, -1, "[decode] -> decode fault detected at 0x%llx / thr: %" PRIu32 ", set to fatal on detect\n", ins_address,
hw_thr);
}
bundle->addInstruction(new VanadisInstructionDecodeFault(ins_address, hw_thr, options));
}
}

uint16_t expand_rvc_int_register(const uint16_t reg_in) const { return reg_in + 8; }
Expand Down

0 comments on commit 9494c59

Please sign in to comment.