Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <[email protected]>

Kconfig

@@ -383,6 +383,14 @@ config FIT_ENABLE_RSASSA_PSS_SUPPORT
 	  Enable this to support the pss padding algorithm as described
 	  in the rfc8017 (https://tools.ietf.org/html/rfc8017).
 
+config FIT_CIPHER
+	bool "Enable ciphering data in a FIT uImages"
+	depends on DM
+	select AES
+	help
+	  Enable the feature of data ciphering/unciphering in the tool mkimage
+	  and in the u-boot support of the FIT image.
+
 config FIT_VERBOSE
 	bool "Show verbose messages when FIT images fail"
 	help

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -125,7 +125,6 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
 #define HWA_CGA_M2_CLK_SEL	0x00000007
 #define HWA_CGA_M2_CLK_SHIFT	0
 #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
@@ -148,11 +147,10 @@ void get_sys_info(struct sys_info *sys_info)
 		break;
 #endif
 	default:
-		printf("Error: Unknown peripheral clock select!\n");
+		printf("Error: Unknown cluster group A mux 2 clock select!\n");
 		break;
 	}
 #endif
-#endif
 
 #if defined(CONFIG_FSL_IFC)
 	sys_info->freq_localbus = sys_info->freq_systembus /
@@ -179,28 +177,21 @@ unsigned long get_qman_freq(void)
 int get_clocks(void)
 {
 	struct sys_info sys_info;
-
+#ifdef CONFIG_FSL_ESDHC
+	u32 clock = 0;
+#endif
 	get_sys_info(&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
 	gd->mem_clk = sys_info.freq_ddrbus;
-
 #ifdef CONFIG_FSL_ESDHC
-#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
-#if defined(CONFIG_TARGET_LS1046ARDB)
-	gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
-#endif
-#if defined(CONFIG_TARGET_LS1043ARDB)
-	gd->arch.sdhc_clk = sys_info.freq_cga_m2;
-#endif
-#if defined(CONFIG_TARGET_LS1012ARDB)
-	gd->arch.sdhc_clk = sys_info.freq_systembus;
-#endif
-#else
-	gd->arch.sdhc_clk = (sys_info.freq_systembus /
-			CONFIG_SYS_FSL_PCLK_DIV) /
-			CONFIG_SYS_FSL_SDHC_CLK_DIV;
+#if defined(CONFIG_ARCH_LS1012A)
+	clock = sys_info.freq_systembus;
+#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+	clock = sys_info.freq_cga_m2;
 #endif
+	gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
+	gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif
 	if (gd->cpu_clk != 0)
 		return 0;

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -160,33 +160,31 @@ void get_sys_info(struct sys_info *sys_info)
 		break;
 	}
 #endif
-#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
-	sys_info->freq_cga_m2 = sys_info->freq_systembus;
-#endif
 }
 
 int get_clocks(void)
 {
 	struct sys_info sys_info;
+#ifdef CONFIG_FSL_ESDHC
+	u32 clock = 0;
+#endif
 	get_sys_info(&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
 	gd->mem_clk = sys_info.freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 #endif
-#if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
-#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
-	gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
-#endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
-	gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+
+#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
+	clock = sys_info.freq_cga_m2;
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
+	clock = sys_info.freq_systembus;
 #endif
-#else
+	gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 	gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif
-#endif /* defined(CONFIG_FSL_ESDHC) */
 
 	if (gd->cpu_clk != 0)
 		return 0;

arch/arm/include/asm/global_data.h

@@ -13,6 +13,10 @@ struct arch_global_data {
 	u32 sdhc_clk;
 #endif
 
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_per_clk;
+#endif
+
 #if defined(CONFIG_U_QE)
 	u32 qe_clk;
 	u32 brg_clk;

arch/arm/mach-tegra/tegra20/crypto.c

@@ -39,34 +39,35 @@ static void left_shift_vector(u8 *in, u8 *out, int size)
 /**
  * Sign a block of data, putting the result into dst.
  *
- * \param key			Input AES key, length AES_KEY_LENGTH
+ * \param key			Input AES key, length AES128_KEY_LENGTH
  * \param key_schedule		Expanded key to use
  * \param src			Source data of length 'num_aes_blocks' blocks
- * \param dst			Destination buffer, length AES_KEY_LENGTH
+ * \param dst			Destination buffer, length AES128_KEY_LENGTH
  * \param num_aes_blocks	Number of AES blocks to encrypt
  */
 static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
 			u32 num_aes_blocks)
 {
-	u8 tmp_data[AES_KEY_LENGTH];
-	u8 iv[AES_KEY_LENGTH] = {0};
-	u8 left[AES_KEY_LENGTH];
-	u8 k1[AES_KEY_LENGTH];
+	u8 tmp_data[AES128_KEY_LENGTH];
+	u8 iv[AES128_KEY_LENGTH] = {0};
+	u8 left[AES128_KEY_LENGTH];
+	u8 k1[AES128_KEY_LENGTH];
 	u8 *cbc_chain_data;
 	unsigned i;
 
 	cbc_chain_data = zero_key;	/* Convenient array of 0's for IV */
 
 	/* compute K1 constant needed by AES-CMAC calculation */
-	for (i = 0; i < AES_KEY_LENGTH; i++)
+	for (i = 0; i < AES128_KEY_LENGTH; i++)
 		tmp_data[i] = 0;
 
-	aes_cbc_encrypt_blocks(key_schedule, iv, tmp_data, left, 1);
+	aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv,
+			       tmp_data, left, 1);
 
 	left_shift_vector(left, k1, sizeof(left));
 
 	if ((left[0] >> 7) != 0) /* get MSB of L */
-		k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB;
+		k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB;
 
 	/* compute the AES-CMAC value */
 	for (i = 0; i < num_aes_blocks; i++) {
@@ -78,47 +79,49 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
 			aes_apply_cbc_chain_data(tmp_data, k1, tmp_data);
 
 		/* encrypt the AES block */
-		aes_encrypt(tmp_data, key_schedule, dst);
+		aes_encrypt(AES128_KEY_LENGTH, tmp_data,
+			    key_schedule, dst);
 
 		debug("sign_obj: block %d of %d\n", i, num_aes_blocks);
 
 		/* Update pointers for next loop. */
 		cbc_chain_data = dst;
-		src += AES_KEY_LENGTH;
+		src += AES128_KEY_LENGTH;
 	}
 }
 
 /**
  * Encrypt and sign a block of data (depending on security mode).
  *
- * \param key		Input AES key, length AES_KEY_LENGTH
+ * \param key		Input AES key, length AES128_KEY_LENGTH
  * \param oper		Security operations mask to perform (enum security_op)
  * \param src		Source data
  * \param length	Size of source data
- * \param sig_dst	Destination address for signature, AES_KEY_LENGTH bytes
+ * \param sig_dst	Destination address for signature, AES128_KEY_LENGTH bytes
  */
 static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
 			    u32 length, u8 *sig_dst)
 {
 	u32 num_aes_blocks;
-	u8 key_schedule[AES_EXPAND_KEY_LENGTH];
-	u8 iv[AES_KEY_LENGTH] = {0};
+	u8 key_schedule[AES128_EXPAND_KEY_LENGTH];
+	u8 iv[AES128_KEY_LENGTH] = {0};
 
 	debug("encrypt_and_sign: length = %d\n", length);
 
 	/*
 	 * The only need for a key is for signing/checksum purposes, so
 	 * if not encrypting, expand a key of 0s.
 	 */
-	aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, key_schedule);
+	aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key,
+		       AES128_KEY_LENGTH, key_schedule);
 
-	num_aes_blocks = (length + AES_KEY_LENGTH - 1) / AES_KEY_LENGTH;
+	num_aes_blocks = (length + AES128_KEY_LENGTH - 1) / AES128_KEY_LENGTH;
 
 	if (oper & SECURITY_ENCRYPT) {
 		/* Perform this in place, resulting in src being encrypted. */
 		debug("encrypt_and_sign: begin encryption\n");
-		aes_cbc_encrypt_blocks(key_schedule, iv, src, src,
-				       num_aes_blocks);
+		aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src,
+				       src, num_aes_blocks);
 		debug("encrypt_and_sign: end encryption\n");
 	}
 

arch/powerpc/cpu/mpc85xx/speed.c

@@ -69,8 +69,7 @@ void get_sys_info(sys_info_t *sys_info)
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
-	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@@ -450,48 +449,6 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 #endif
 
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-#if defined(CONFIG_ARCH_T2080)
-#define ESDHC_CLK_SEL	0x00000007
-#define ESDHC_CLK_SHIFT	0
-#define ESDHC_CLK_RCWSR	15
-#else	/* Support T1040 T1024 by now */
-#define ESDHC_CLK_SEL	0xe0000000
-#define ESDHC_CLK_SHIFT	29
-#define ESDHC_CLK_RCWSR	7
-#endif
-	rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
-	switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
-	case 1:
-		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
-		break;
-	case 2:
-		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
-		break;
-	case 3:
-		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
-		break;
-#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
-	case 4:
-		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
-		break;
-#if defined(CONFIG_ARCH_T2080)
-	case 5:
-		sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
-		break;
-#endif
-	case 6:
-		sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
-		break;
-	case 7:
-		sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
-		break;
-#endif
-	default:
-		sys_info->freq_sdhc = 0;
-		printf("Error: Unknown SDHC peripheral clock select!\n");
-	}
-#endif
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
@@ -673,15 +630,11 @@ int get_clocks (void)
 	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
-#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-	gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
-#else
 #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
 	gd->arch.sdhc_clk = gd->bus_clk;
 #else
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
-#endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
 #if defined(CONFIG_CPM2)

arch/powerpc/include/asm/config_mpc85xx.h

@@ -331,9 +331,6 @@
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV	1
 #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
-#define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
-					    per rcw field value */
-#define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -362,8 +359,6 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FM1_CLK		0
-#define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
-					    per rcw field value */
 #define CONFIG_QBMAN_CLK_DIV		1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@@ -402,9 +397,6 @@
 #define CONFIG_PME_PLAT_CLK_DIV		1
 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK		0
-#define CONFIG_SYS_SDHC_CLK		1/* Select SDHC CLK begining from PLL2
-					    per rcw field value */
-#define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000

arch/powerpc/include/asm/global_data.h

@@ -14,6 +14,7 @@
 struct arch_global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
+	u32 sdhc_per_clk;
 #if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
 	u8 sdhc_adapter;
 #endif

board/solidrun/clearfog/README

@@ -20,12 +20,6 @@ of "/dev/sdX" here!
 Install U-Boot on eMMC:
 -----------------------
 
-The ROM loads the bootloader from eMMC first boot partition at offset 0. This
-is unlike load from SD card that is at offset 512. As a result, the offset of
-the main U-Boot image on the eMMC boot partition changes. Set
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from
-the correct location.
-
 To make SPL load the main U-Boot image from the eMMC boot partition enable
 eMMC boot acknowledgement and boot partition with the following U-Boot
 command: