arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python …

…& Java bindings accordingly
Kozoro · Aug 13, 2014 · 7c089fd · 7c089fd
1 parent b52f11f
commit 7c089fd
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Showing 6 changed files with 9 additions and 4 deletions.
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
@@ -364,7 +364,7 @@ static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
 		uint64_t Address, const void *Decoder);
 
 // Hacky: enable all features for disassembler
-uint64_t ARM_getFeatureBits(int mode)
+uint64_t ARM_getFeatureBits(unsigned int mode)
 {
 	uint64_t Bits = (uint64_t)-1;	// everything by default
 
@@ -377,7 +377,8 @@ uint64_t ARM_getFeatureBits(int mode)
 	//Bits &= ~ARM_HasV8Ops;
 	//Bits &= ~ARM_HasV6Ops;
 
-	Bits &= (~ARM_FeatureMClass);
+	if ((mode & CS_MODE_MCLASS) == 0)
+		Bits &= (~ARM_FeatureMClass);
 
 	// some features are mutually exclusive
 	if (mode & CS_MODE_THUMB) {

diff --git a/arch/ARM/ARMDisassembler.h b/arch/ARM/ARMDisassembler.h
@@ -13,6 +13,6 @@ bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst
 
 bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
 
-uint64_t ARM_getFeatureBits(int mode);
+uint64_t ARM_getFeatureBits(unsigned int mode);
 
 #endif
diff --git a/arch/ARM/ARMModule.c b/arch/ARM/ARMModule.c
@@ -15,7 +15,7 @@ static cs_err init(cs_struct *ud)
 
 	// verify if requested mode is valid
 	if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM |
-				CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
+				CS_MODE_MCLASS | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
 		return CS_ERR_MODE;
 
 	mri = cs_mem_malloc(sizeof(*mri));

diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java
@@ -284,6 +284,7 @@ public NativeLong cs_disasm_ex(NativeLong handle, byte[] code, NativeLong code_l
   public static final int CS_MODE_32 = 1 << 2;
   public static final int CS_MODE_64 = 1 << 3;
   public static final int CS_MODE_THUMB = 1 << 4;	  // ARM's Thumb mode, including Thumb-2
+  public static final int CS_MODE_MCLASS = 1 << 5;	  // ARM's Cortex-M series
   public static final int CS_MODE_MICRO = 1 << 4;	  // MicroMips mode (Mips arch)
   public static final int CS_MODE_N64 = 1 << 5;	      // Nintendo-64 mode (Mips arch)
   public static final int CS_MODE_BIG_ENDIAN = 1 << 31;

diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
@@ -36,6 +36,7 @@
     'CS_MODE_64',
     'CS_MODE_ARM',
     'CS_MODE_THUMB',
+    'CS_MODE_MCLASS',
     'CS_MODE_MICRO',
     'CS_MODE_N64',
     'CS_MODE_V9',
@@ -96,6 +97,7 @@
 CS_MODE_32 = (1 << 2)          # 32-bit mode (for X86, Mips)
 CS_MODE_64 = (1 << 3)          # 64-bit mode (for X86, Mips)
 CS_MODE_THUMB = (1 << 4)       # ARM's Thumb mode, including Thumb-2
+CS_MODE_MCLASS = (1 << 5)      # ARM's Cortex-M series
 CS_MODE_MICRO = (1 << 4)       # MicroMips mode (MIPS architecture)
 CS_MODE_N64 = (1 << 5)         # Nintendo-64 mode (MIPS architecture)
 CS_MODE_V9 = (1 << 4)          # Nintendo-64 mode (MIPS architecture)

diff --git a/include/capstone.h b/include/capstone.h
@@ -70,6 +70,7 @@ typedef enum cs_mode {
 	CS_MODE_32 = 1 << 2,	// 32-bit mode
 	CS_MODE_64 = 1 << 3,	// 64-bit mode
 	CS_MODE_THUMB = 1 << 4,	// ARM's Thumb mode, including Thumb-2
+	CS_MODE_MCLASS = 1 << 5,	// ARM's Cortex-M series
 	CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
 	CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
 	CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)