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Merge branch 'renesas-bit-twiddling'
Sergei Shtylyov says: ==================== Factor out register bit twiddling in the Renesas Ethernet drivers Here's a set of 2 patches against DaveM's 'net-next.git' repo. We factor out the often repeated pattern of reading a register, AND'ing and/or OR'ing some bits, and then writing the value back. [1/2] ravb: factor out register bit twiddling code [2/2] sh_eth: factor out register bit twiddling code ==================== Signed-off-by: David S. Miller <[email protected]>
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@@ -2,7 +2,7 @@ | |
* | ||
* Copyright (C) 2014-2015 Renesas Electronics Corporation | ||
* Copyright (C) 2015 Renesas Solutions Corp. | ||
* Copyright (C) 2015 Cogent Embedded, Inc. <[email protected]> | ||
* Copyright (C) 2015-2016 Cogent Embedded, Inc. <[email protected]> | ||
* | ||
* Based on the SuperH Ethernet driver | ||
* | ||
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@@ -837,6 +837,8 @@ static inline void ravb_write(struct net_device *ndev, u32 data, | |
iowrite32(data, priv->addr + reg); | ||
} | ||
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void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, | ||
u32 set); | ||
int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value); | ||
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irqreturn_t ravb_ptp_interrupt(struct net_device *ndev); | ||
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@@ -2,7 +2,7 @@ | |
* | ||
* Copyright (C) 2014-2015 Renesas Electronics Corporation | ||
* Copyright (C) 2015 Renesas Solutions Corp. | ||
* Copyright (C) 2015 Cogent Embedded, Inc. <[email protected]> | ||
* Copyright (C) 2015-2016 Cogent Embedded, Inc. <[email protected]> | ||
* | ||
* Based on the SuperH Ethernet driver | ||
* | ||
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@@ -42,6 +42,12 @@ | |
NETIF_MSG_RX_ERR | \ | ||
NETIF_MSG_TX_ERR) | ||
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void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, | ||
u32 set) | ||
{ | ||
ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); | ||
} | ||
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int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) | ||
{ | ||
int i; | ||
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@@ -59,8 +65,7 @@ static int ravb_config(struct net_device *ndev) | |
int error; | ||
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/* Set config mode */ | ||
ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, | ||
CCC); | ||
ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); | ||
/* Check if the operating mode is changed to the config mode */ | ||
error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); | ||
if (error) | ||
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@@ -72,13 +77,8 @@ static int ravb_config(struct net_device *ndev) | |
static void ravb_set_duplex(struct net_device *ndev) | ||
{ | ||
struct ravb_private *priv = netdev_priv(ndev); | ||
u32 ecmr = ravb_read(ndev, ECMR); | ||
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if (priv->duplex) /* Full */ | ||
ecmr |= ECMR_DM; | ||
else /* Half */ | ||
ecmr &= ~ECMR_DM; | ||
ravb_write(ndev, ecmr, ECMR); | ||
ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); | ||
} | ||
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static void ravb_set_rate(struct net_device *ndev) | ||
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@@ -131,13 +131,8 @@ static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) | |
{ | ||
struct ravb_private *priv = container_of(ctrl, struct ravb_private, | ||
mdiobb); | ||
u32 pir = ravb_read(priv->ndev, PIR); | ||
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if (set) | ||
pir |= mask; | ||
else | ||
pir &= ~mask; | ||
ravb_write(priv->ndev, pir, PIR); | ||
ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); | ||
} | ||
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/* MDC pin control */ | ||
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@@ -393,9 +388,9 @@ static int ravb_dmac_init(struct net_device *ndev) | |
ravb_ring_format(ndev, RAVB_NC); | ||
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#if defined(__LITTLE_ENDIAN) | ||
ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC); | ||
ravb_modify(ndev, CCC, CCC_BOC, 0); | ||
#else | ||
ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC); | ||
ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); | ||
#endif | ||
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/* Set AVB RX */ | ||
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@@ -418,8 +413,7 @@ static int ravb_dmac_init(struct net_device *ndev) | |
ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); | ||
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/* Setting the control will start the AVB-DMAC process. */ | ||
ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION, | ||
CCC); | ||
ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); | ||
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return 0; | ||
} | ||
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@@ -493,7 +487,7 @@ static void ravb_get_tx_tstamp(struct net_device *ndev) | |
break; | ||
} | ||
} | ||
ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR); | ||
ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); | ||
} | ||
} | ||
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@@ -613,13 +607,13 @@ static bool ravb_rx(struct net_device *ndev, int *quota, int q) | |
static void ravb_rcv_snd_disable(struct net_device *ndev) | ||
{ | ||
/* Disable TX and RX */ | ||
ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR); | ||
ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); | ||
} | ||
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static void ravb_rcv_snd_enable(struct net_device *ndev) | ||
{ | ||
/* Enable TX and RX */ | ||
ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR); | ||
ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); | ||
} | ||
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/* function for waiting dma process finished */ | ||
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@@ -812,8 +806,8 @@ static int ravb_poll(struct napi_struct *napi, int budget) | |
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/* Re-enable RX/TX interrupts */ | ||
spin_lock_irqsave(&priv->lock, flags); | ||
ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0); | ||
ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC); | ||
ravb_modify(ndev, RIC0, mask, mask); | ||
ravb_modify(ndev, TIC, mask, mask); | ||
mmiowb(); | ||
spin_unlock_irqrestore(&priv->lock, flags); | ||
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@@ -852,8 +846,7 @@ static void ravb_adjust_link(struct net_device *ndev) | |
ravb_set_rate(ndev); | ||
} | ||
if (!priv->link) { | ||
ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF, | ||
ECMR); | ||
ravb_modify(ndev, ECMR, ECMR_TXF, 0); | ||
new_state = true; | ||
priv->link = phydev->link; | ||
if (priv->no_avb_link) | ||
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@@ -1393,7 +1386,7 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
desc--; | ||
desc->die_dt = DT_FSTART; | ||
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ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR); | ||
ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); | ||
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priv->cur_tx[q] += NUM_TX_DESC; | ||
if (priv->cur_tx[q] - priv->dirty_tx[q] > | ||
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@@ -1468,15 +1461,10 @@ static void ravb_set_rx_mode(struct net_device *ndev) | |
{ | ||
struct ravb_private *priv = netdev_priv(ndev); | ||
unsigned long flags; | ||
u32 ecmr; | ||
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spin_lock_irqsave(&priv->lock, flags); | ||
ecmr = ravb_read(ndev, ECMR); | ||
if (ndev->flags & IFF_PROMISC) | ||
ecmr |= ECMR_PRM; | ||
else | ||
ecmr &= ~ECMR_PRM; | ||
ravb_write(ndev, ecmr, ECMR); | ||
ravb_modify(ndev, ECMR, ECMR_PRM, | ||
ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); | ||
mmiowb(); | ||
spin_unlock_irqrestore(&priv->lock, flags); | ||
} | ||
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@@ -1804,14 +1792,12 @@ static int ravb_probe(struct platform_device *pdev) | |
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/* Set AVB config mode */ | ||
if (chip_id == RCAR_GEN2) { | ||
ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | | ||
CCC_OPC_CONFIG, CCC); | ||
ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); | ||
/* Set CSEL value */ | ||
ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | | ||
CCC_CSEL_HPB, CCC); | ||
ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); | ||
} else { | ||
ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | | ||
CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB, CCC); | ||
ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | | ||
CCC_GAC | CCC_CSEL_HPB); | ||
} | ||
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/* Set CSEL value */ | ||
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@@ -1824,7 +1810,7 @@ static int ravb_probe(struct platform_device *pdev) | |
goto out_release; | ||
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/* Request GTI loading */ | ||
ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR); | ||
ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); | ||
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/* Allocate descriptor base address table */ | ||
priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; | ||
|
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|
@@ -2,7 +2,7 @@ | |
* | ||
* Copyright (C) 2013-2015 Renesas Electronics Corporation | ||
* Copyright (C) 2015 Renesas Solutions Corp. | ||
* Copyright (C) 2015 Cogent Embedded, Inc. <[email protected]> | ||
* Copyright (C) 2015-2016 Cogent Embedded, Inc. <[email protected]> | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License as published by | ||
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@@ -21,7 +21,7 @@ static int ravb_ptp_tcr_request(struct ravb_private *priv, u32 request) | |
if (error) | ||
return error; | ||
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ravb_write(ndev, ravb_read(ndev, GCCR) | request, GCCR); | ||
ravb_modify(ndev, GCCR, request, request); | ||
return ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ); | ||
} | ||
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@@ -185,7 +185,6 @@ static int ravb_ptp_extts(struct ptp_clock_info *ptp, | |
ptp.info); | ||
struct net_device *ndev = priv->ndev; | ||
unsigned long flags; | ||
u32 gic; | ||
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if (req->index) | ||
return -EINVAL; | ||
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@@ -195,12 +194,7 @@ static int ravb_ptp_extts(struct ptp_clock_info *ptp, | |
priv->ptp.extts[req->index] = on; | ||
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spin_lock_irqsave(&priv->lock, flags); | ||
gic = ravb_read(ndev, GIC); | ||
if (on) | ||
gic |= GIC_PTCE; | ||
else | ||
gic &= ~GIC_PTCE; | ||
ravb_write(ndev, gic, GIC); | ||
ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); | ||
mmiowb(); | ||
spin_unlock_irqrestore(&priv->lock, flags); | ||
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@@ -216,7 +210,6 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp, | |
struct ravb_ptp_perout *perout; | ||
unsigned long flags; | ||
int error = 0; | ||
u32 gic; | ||
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if (req->index) | ||
return -EINVAL; | ||
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@@ -248,9 +241,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp, | |
error = ravb_ptp_update_compare(priv, (u32)start_ns); | ||
if (!error) { | ||
/* Unmask interrupt */ | ||
gic = ravb_read(ndev, GIC); | ||
gic |= GIC_PTME; | ||
ravb_write(ndev, gic, GIC); | ||
ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); | ||
} | ||
} else { | ||
spin_lock_irqsave(&priv->lock, flags); | ||
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@@ -259,9 +250,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp, | |
perout->period = 0; | ||
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/* Mask interrupt */ | ||
gic = ravb_read(ndev, GIC); | ||
gic &= ~GIC_PTME; | ||
ravb_write(ndev, gic, GIC); | ||
ravb_modify(ndev, GIC, GIC_PTME, 0); | ||
} | ||
mmiowb(); | ||
spin_unlock_irqrestore(&priv->lock, flags); | ||
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@@ -331,7 +320,6 @@ void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev) | |
{ | ||
struct ravb_private *priv = netdev_priv(ndev); | ||
unsigned long flags; | ||
u32 gccr; | ||
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priv->ptp.info = ravb_ptp_info; | ||
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@@ -340,8 +328,7 @@ void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev) | |
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spin_lock_irqsave(&priv->lock, flags); | ||
ravb_wait(ndev, GCCR, GCCR_TCR, GCCR_TCR_NOREQ); | ||
gccr = ravb_read(ndev, GCCR) & ~GCCR_TCSS; | ||
ravb_write(ndev, gccr | GCCR_TCSS_ADJGPTP, GCCR); | ||
ravb_modify(ndev, GCCR, GCCR_TCSS, GCCR_TCSS_ADJGPTP); | ||
mmiowb(); | ||
spin_unlock_irqrestore(&priv->lock, flags); | ||
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