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Merge branch 'arm/fixes' into arm/soc
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Merging in the last batch of fixes that didn't go in before previous
release, just a few smaller DT fixups and a MAINTAINERS update

* arm/fixes: (29 commits)
  MAINTAINERS: Add myself as TEE subsystem reviewer
  ARM: dts: ux500: Fix LED probing
  arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory
  arm64: dts: allwinner: a64-sopine-baseboard: change RGMII mode to TXID
  arm64: meson: select COMMON_CLK
  soc: amlogic: meson-clk-measure: remove redundant dev_err call in meson_msr_probe()
  ARM: dts: qcom: sdx55-telit: Represent secure-regions as 64-bit elements
  ARM: dts: qcom: sdx55-t55: Represent secure-regions as 64-bit elements
  ARM: dts: sun8i: h3: orangepi-plus: Fix ethernet phy-mode
  ARM: dts: imx: emcon-avari: Fix nxp,pca8574 #gpio-cells
  ARM: dts: imx7d-pico: Fix the 'tuning-step' property
  ARM: dts: imx7d-meerkat96: Fix the 'tuning-step' property
  arm64: dts: freescale: sl28: var1: fix RGMII clock and voltage
  arm64: dts: freescale: sl28: var4: fix RGMII clock and voltage
  ARM: imx: pm-imx27: Include "common.h"
  arm64: dts: zii-ultra: fix 12V_MAIN voltage
  arm64: dts: zii-ultra: remove second GEN_3V3 regulator instance
  arm64: dts: ls1028a: fix memory node
  optee: use export_uuid() to copy client UUID
  arm64: dts: ti: k3*: Introduce reg definition for interrupt routers
  ...
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@olofj
olofj committed Jul 9, 2021
2 parents 95ef715 + 048c958 commit 42accad
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Showing 32 changed files with 108 additions and 107 deletions.
1 change: 1 addition & 0 deletions MAINTAINERS
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Expand Up @@ -17921,6 +17921,7 @@ F: include/media/i2c/tw9910.h

TEE SUBSYSTEM
M: Jens Wiklander <[email protected]>
R: Sumit Garg <[email protected]>
L: [email protected]
S: Maintained
F: Documentation/staging/tee.rst
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6 changes: 5 additions & 1 deletion arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
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Expand Up @@ -105,9 +105,13 @@
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
phy-supply = <&sw2_reg>;
phy-handle = <&ethphy0>;
status = "okay";

fixed-link {
speed = <1000>;
full-duplex;
};

mdio {
#address-cells = <1>;
#size-cells = <0>;
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12 changes: 12 additions & 0 deletions arch/arm/boot/dts/imx6q-dhcom-som.dtsi
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Expand Up @@ -406,6 +406,18 @@
vin-supply = <&sw1_reg>;
};

&reg_pu {
vin-supply = <&sw1_reg>;
};

&reg_vdd1p1 {
vin-supply = <&sw2_reg>;
};

&reg_vdd2p5 {
vin-supply = <&sw2_reg>;
};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
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2 changes: 1 addition & 1 deletion arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi
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Expand Up @@ -126,7 +126,7 @@
compatible = "nxp,pca8574";
reg = <0x3a>;
gpio-controller;
#gpio-cells = <1>;
#gpio-cells = <2>;
};
};

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2 changes: 1 addition & 1 deletion arch/arm/boot/dts/imx7d-meerkat96.dts
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Expand Up @@ -193,7 +193,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
keep-power-in-suspend;
tuning-step = <2>;
fsl,tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v;
broken-cd;
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2 changes: 1 addition & 1 deletion arch/arm/boot/dts/imx7d-pico.dtsi
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Expand Up @@ -351,7 +351,7 @@
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
bus-width = <4>;
tuning-step = <2>;
fsl,tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
wakeup-source;
no-1-8-v;
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2 changes: 1 addition & 1 deletion arch/arm/boot/dts/qcom-sdx55-t55.dts
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Expand Up @@ -250,7 +250,7 @@
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* efs2 partition is secured */
secure-regions = <0x500000 0xb00000>;
secure-regions = /bits/ 64 <0x500000 0xb00000>;
};
};

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4 changes: 2 additions & 2 deletions arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
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Expand Up @@ -250,8 +250,8 @@
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* ico and efs2 partitions are secured */
secure-regions = <0x500000 0x500000
0xa00000 0xb00000>;
secure-regions = /bits/ 64 <0x500000 0x500000
0xa00000 0xb00000>;
};
};

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7 changes: 7 additions & 0 deletions arch/arm/boot/dts/ste-href.dtsi
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Expand Up @@ -4,6 +4,7 @@
*/

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include "ste-href-family-pinctrl.dtsi"

/ {
Expand Down Expand Up @@ -64,17 +65,20 @@
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
};
lp5521@34 {
Expand All @@ -88,16 +92,19 @@
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
color = <LED_COLOR_ID_BLUE>;
};
};
bh1780@29 {
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2 changes: 1 addition & 1 deletion arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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Expand Up @@ -85,7 +85,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";

status = "okay";
};
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1 change: 1 addition & 0 deletions arch/arm/mach-imx/pm-imx27.c
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Expand Up @@ -12,6 +12,7 @@
#include <linux/suspend.h>
#include <linux/io.h>

#include "common.h"
#include "hardware.h"

static int mx27_suspend_enter(suspend_state_t state)
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1 change: 1 addition & 0 deletions arch/arm64/Kconfig.platforms
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Expand Up @@ -166,6 +166,7 @@ config ARCH_MEDIATEK

config ARCH_MESON
bool "Amlogic Platforms"
select COMMON_CLK
select MESON_IRQ_GPIO
help
This enables support for the arm64 based Amlogic SoCs
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2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
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Expand Up @@ -79,7 +79,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dc1sw>;
status = "okay";
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3 changes: 2 additions & 1 deletion arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
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Expand Up @@ -46,7 +46,8 @@
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
vddio-supply = <&vddh>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;

vddio: vddio-regulator {
regulator-name = "VDDIO";
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5 changes: 2 additions & 3 deletions arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
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Expand Up @@ -31,11 +31,10 @@
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;

qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;

vddio-supply = <&vddh>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;

vddio: vddio-regulator {
regulator-name = "VDDIO";
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4 changes: 2 additions & 2 deletions arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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Expand Up @@ -197,8 +197,8 @@
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
};

dcfg: syscon@1e00000 {
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10 changes: 5 additions & 5 deletions arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
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Expand Up @@ -88,11 +88,11 @@
pinctrl-0 = <&pinctrl_codec2>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
HPVDD-supply = <&reg_gen_3p3>;
SPRVDD-supply = <&reg_gen_3p3>;
SPLVDD-supply = <&reg_gen_3p3>;
AVDD-supply = <&reg_gen_3p3>;
IOVDD-supply = <&reg_gen_3p3>;
DVDD-supply = <&vgen4_reg>;
reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
};
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23 changes: 7 additions & 16 deletions arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
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Expand Up @@ -45,8 +45,8 @@
reg_12p0_main: regulator-12p0-main {
compatible = "regulator-fixed";
regulator-name = "12V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};

Expand Down Expand Up @@ -77,15 +77,6 @@
regulator-always-on;
};

reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
vin-supply = <&reg_3p3_main>;
regulator-name = "GEN_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};

reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
Expand Down Expand Up @@ -415,11 +406,11 @@
pinctrl-0 = <&pinctrl_codec1>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
HPVDD-supply = <&reg_gen_3p3>;
SPRVDD-supply = <&reg_gen_3p3>;
SPLVDD-supply = <&reg_gen_3p3>;
AVDD-supply = <&reg_gen_3p3>;
IOVDD-supply = <&reg_gen_3p3>;
DVDD-supply = <&vgen4_reg>;
reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
};
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2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/rockchip/rk3399.dtsi
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Expand Up @@ -227,7 +227,7 @@
<&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1",
"pcie-phy-2", "pcie-phy-3";
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
<0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
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11 changes: 6 additions & 5 deletions arch/arm64/boot/dts/ti/k3-am64-main.dtsi
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Expand Up @@ -42,12 +42,12 @@
};
};

dmss: dmss {
dmss: bus@48000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;

ti,sci-dev-id = <25>;

Expand Down Expand Up @@ -134,7 +134,7 @@
};
};

dmsc: dmsc@44043000 {
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
Expand All @@ -148,7 +148,7 @@
#power-domain-cells = <2>;
};

k3_clks: clocks {
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
Expand Down Expand Up @@ -373,8 +373,9 @@
clocks = <&k3_clks 145 0>;
};

main_gpio_intr: interrupt-controller0 {
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
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3 changes: 2 additions & 1 deletion arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
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Expand Up @@ -74,8 +74,9 @@
clocks = <&k3_clks 148 0>;
};

mcu_gpio_intr: interrupt-controller1 {
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
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10 changes: 6 additions & 4 deletions arch/arm64/boot/dts/ti/k3-am65-main.dtsi
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Expand Up @@ -433,8 +433,9 @@
#phy-cells = <0>;
};

intr_main_gpio: interrupt-controller0 {
intr_main_gpio: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x0 0x00a00000 0x0 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
Expand All @@ -444,18 +445,19 @@
ti,interrupt-ranges = <0 392 32>;
};

main-navss {
main_navss: bus@30800000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
dma-coherent;
dma-ranges;

ti,sci-dev-id = <118>;

intr_main_navss: interrupt-controller1 {
intr_main_navss: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x0 0x310e0000 0x0 0x2000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
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4 changes: 2 additions & 2 deletions arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
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Expand Up @@ -116,11 +116,11 @@
};
};

mcu-navss {
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;

Expand Down
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