A SystemC productivity library: https://minres.github.io/SystemC-Components/

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.

Native Rust implementation of the FST waveform format from GTKWave.

Build your hardware, easily!

A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.

A FPGA friendly 32 bit RISC-V CPU implementation

Erlang foreign function interface.

Cuneiform worker implementation

The Verilog source code for DRUM approximate multiplier. A configurable approximate multiplier with features such as dynamic range, and unbiased error distribution.

Handle Fast Signal Traces (fst) in Python

RISC-V instruction set simulator built for education

Recipes and build machinery for the biggest Emacs package repo

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

WAL enables programmable waveform analysis.

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

SpinalHDL core

nextpnr portable FPGA place and route tool

A Python toolbox for building complex digital hardware