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1. 75-DAYS-RTL 75-DAYS-RTL Public

   Verilog

2. AHB-to-APB-Bridge AHB-to-APB-Bridge Public

   This repository contains the work done during the project under taken as a part of PG-Diploma in VLSI. The project title is "Design & Verification of AHB to APB Bridge". For the scope of this proje…

   Verilog

3. Sync-FIFO-Memory Sync-FIFO-Memory Public

   The FIFO memory efficiently managed data flow between input and output interfaces while ensuring synchronous operation. Resulting in reliable data buffering and transfer.

   Verilog