Stars
TimeTagger FPGALink Reference
Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
Run Windows Applications on Linux as if they are native, Use linux applications to launch files files located in windows vm without needing to install applications on vm. With easy to use configura…
Get your Advent of Code data with a single import statement
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
Project F brings FPGAs to life with exciting open-source designs you can build on.
Betrusted main SoC design
A collection of handy Bash One-Liners and terminal tricks for data processing and Linux system maintenance.
a structural diff that understands syntax 🟥🟩
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
An abstract language model of VHDL written in Python.
Filters to block and remove copycat-websites from DuckDuckGo, Google and other search engines. Specific to dev websites like StackOverflow or GitHub.
List of projects that provide terminal user interfaces
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Create agents that monitor and act on your behalf. Your agents are standing by!
Recipes for using Python's pandas library
A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI
A Reddit client for Android
Modern C++ solutions for Advent of Code 2021
Build Customized FPGA Implementations for Vivado
clavin-xlnx / hw
Forked from nvdla/hwRTL, Cmodel, and testbench for NVDLA