x86/mce: address violations of MISRA C Rule 16.3

Add missing break statements to address violations of MISRA C Rule 16.3: "An unconditional `break' statement shall terminate every switch-clause". No functional change. Signed-off-by: Federico Serafini <[email protected]> Reviewed-by: Stefano Stabellini <[email protected]> Acked-by: Jan Beulich <[email protected]>
Mu-L · Jul 30, 2024 · 20716a4 · 20716a4
1 parent 2c9044a
commit 20716a4
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diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -201,6 +201,7 @@ static void mcequirk_amd_apply(enum mcequirk_amd_flags flags)
 
     default:
         ASSERT(flags == MCEQUIRK_NONE);
+        break;
     }
 }
 

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -896,6 +896,8 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
             ppin_msr = 0;
         else if ( c == &boot_cpu_data )
             ppin_msr = MSR_PPIN;
+
+        break;
     }
 }
-Original file line number
+Diff line change
@@ Expand Up @@
         default:
             ASSERT(flags == MCEQUIRK_NONE);
+            break;
         }
     }
@@ Expand Down @@