address more reviews

NALAYBUDY · Apr 16, 2021 · 4f58e8e · 4f58e8e
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commit 4f58e8e
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Showing 5 changed files with 23 additions and 27 deletions.
diff --git a/bp_fe/test/tb/bp_fe_icache/testbench.sv b/bp_fe/test/tb/bp_fe_icache/testbench.sv
@@ -245,7 +245,7 @@ module testbench
     ,.reset_i(reset_i)
 
     ,.mem_cmd_i(mem_cmd_lo)
-    ,.mem_cmd_v_i(mem_cmd_ready_and_lo & mem_cmd_v_lo)
+    ,.mem_cmd_v_i(mem_cmd_v_lo)
     ,.mem_cmd_ready_and_o(mem_cmd_ready_and_lo)
 
     ,.mem_resp_o(mem_resp_lo)
@@ -376,7 +376,7 @@ module testbench
      ,.reset_i(reset_i)
 
      ,.mem_cmd_i(mem_cmd_lo)
-     ,.mem_cmd_v_i(mem_cmd_ready_and_lo & mem_cmd_v_lo)
+     ,.mem_cmd_v_i(mem_cmd_v_lo)
      ,.mem_cmd_ready_and_i(mem_cmd_ready_and_lo)
 
      ,.mem_resp_i(mem_resp_lo)

diff --git a/bp_top/src/v/bp_cacc_tile.sv b/bp_top/src/v/bp_cacc_tile.sv
@@ -42,10 +42,10 @@ module bp_cacc_tile
   bp_bedrock_lce_req_msg_s  cce_lce_req_li;
   logic cce_lce_req_v_li, cce_lce_req_yumi_lo;
   bp_bedrock_lce_cmd_msg_s cce_lce_cmd_lo;
-  logic cce_lce_cmd_v_lo, cce_lce_cmd_ready_li;
+  logic cce_lce_cmd_v_lo, cce_lce_cmd_ready_and_li;
 
   bp_bedrock_cce_mem_msg_s cce_io_cmd_lo;
-  logic cce_io_cmd_v_lo, cce_io_cmd_ready_li;
+  logic cce_io_cmd_v_lo, cce_io_cmd_ready_and_li;
   bp_bedrock_cce_mem_msg_s cce_io_resp_li;
   logic cce_io_resp_v_li, cce_io_resp_yumi_lo;
 
@@ -89,11 +89,11 @@ module bp_cacc_tile
 
      ,.lce_cmd_o(cce_lce_cmd_lo)
      ,.lce_cmd_v_o(cce_lce_cmd_v_lo)
-     ,.lce_cmd_ready_then_i(cce_lce_cmd_ready_li)
+     ,.lce_cmd_ready_then_i(cce_lce_cmd_ready_and_li)
 
      ,.io_cmd_o(cce_io_cmd_lo)
      ,.io_cmd_v_o(cce_io_cmd_v_lo)
-     ,.io_cmd_ready_then_i(cce_io_cmd_ready_li)
+     ,.io_cmd_ready_then_i(cce_io_cmd_ready_and_li)
 
      ,.io_resp_i(cce_io_resp_li)
      ,.io_resp_v_i(cce_io_resp_v_li)
@@ -229,7 +229,7 @@ module bp_cacc_tile
 
      ,.packet_i(cce_lce_cmd_packet_lo)
      ,.v_i(cce_lce_cmd_v_lo)
-     ,.ready_o(cce_lce_cmd_ready_li)
+     ,.ready_o(cce_lce_cmd_ready_and_li)
 
      ,.link_i(cce_lce_cmd_link_li)
      ,.link_o(cce_lce_cmd_link_lo)
@@ -274,7 +274,7 @@ module bp_cacc_tile
 
          ,.io_cmd_i(cce_io_cmd_lo)
          ,.io_cmd_v_i(cce_io_cmd_v_lo)
-         ,.io_cmd_ready_o(cce_io_cmd_ready_li)
+         ,.io_cmd_ready_o(cce_io_cmd_ready_and_li)
 
          ,.io_resp_o(cce_io_resp_li)
          ,.io_resp_v_o(cce_io_resp_v_li)

diff --git a/bp_top/src/v/bp_io_tile.sv b/bp_top/src/v/bp_io_tile.sv
@@ -39,14 +39,14 @@ module bp_io_tile
   `declare_bp_memory_map(paddr_width_p, caddr_width_p);
 
   bp_bedrock_lce_req_msg_s  cce_lce_req_li, lce_lce_req_lo;
-  logic cce_lce_req_v_li, cce_lce_req_yumi_lo, lce_lce_req_v_lo, lce_lce_req_ready_li;
+  logic cce_lce_req_v_li, cce_lce_req_yumi_lo, lce_lce_req_v_lo, lce_lce_req_ready_and_li;
   bp_bedrock_lce_cmd_msg_s cce_lce_cmd_lo, lce_lce_cmd_li;
   logic cce_lce_cmd_v_lo, cce_lce_cmd_ready_li, lce_lce_cmd_v_li, lce_lce_cmd_yumi_lo;
 
   bp_bedrock_cce_mem_msg_s cce_io_cmd_lo, lce_io_cmd_li;
   logic cce_io_cmd_v_lo, cce_io_cmd_ready_li, lce_io_cmd_v_li, lce_io_cmd_yumi_lo;
   bp_bedrock_cce_mem_msg_s cce_io_resp_li, lce_io_resp_lo;
-  logic cce_io_resp_v_li, cce_io_resp_yumi_lo, lce_io_resp_v_lo, lce_io_resp_ready_li;
+  logic cce_io_resp_v_li, cce_io_resp_yumi_lo, lce_io_resp_v_lo, lce_io_resp_ready_and_li;
 
   logic reset_r;
   always_ff @(posedge clk_i)
@@ -79,11 +79,11 @@ module bp_io_tile
 
      ,.io_resp_o(lce_io_resp_lo)
      ,.io_resp_v_o(lce_io_resp_v_lo)
-     ,.io_resp_ready_then_i(lce_io_resp_ready_li)
+     ,.io_resp_ready_then_i(lce_io_resp_ready_and_li)
 
      ,.lce_req_o(lce_lce_req_lo)
      ,.lce_req_v_o(lce_lce_req_v_lo)
-     ,.lce_req_ready_then_i(lce_lce_req_ready_li)
+     ,.lce_req_ready_then_i(lce_lce_req_ready_and_li)
 
      ,.lce_cmd_i(lce_lce_cmd_li)
      ,.lce_cmd_v_i(lce_lce_cmd_v_li)
@@ -140,7 +140,7 @@ module bp_io_tile
 
      ,.packet_i(lce_req_packet_lo)
      ,.v_i(lce_lce_req_v_lo)
-     ,.ready_o(lce_lce_req_ready_li)
+     ,.ready_o(lce_lce_req_ready_and_li)
 
      ,.link_i(lce_req_link_i)
      ,.link_o(lce_req_link_o)
@@ -225,7 +225,7 @@ module bp_io_tile
 
      ,.mem_resp_i(lce_io_resp_lo)
      ,.mem_resp_v_i(lce_io_resp_v_lo)
-     ,.mem_resp_ready_and_o(lce_io_resp_ready_li)
+     ,.mem_resp_ready_and_o(lce_io_resp_ready_and_li)
 
      ,.my_cord_i(io_noc_cord_width_p'(my_did_i))
      ,.my_cid_i('0)

diff --git a/bp_top/src/v/bp_loopback.sv b/bp_top/src/v/bp_loopback.sv
@@ -33,10 +33,6 @@ module bp_cce_loopback
   assign mem_cmd_cast_i = mem_cmd_i;
   assign mem_resp_o = mem_resp_cast_o;
 
-  // NOTE: one fifo comments imply that input is ready->valid, but implementation
-  // is actually ready&valid. Ready comes directly from current state of full_r
-  // register. Valid_i is ignored if fifo is full. Data captured on v_i & ready_o.
-  // Interface can be used ready->valid though, but penalty is cycle time limit
   bsg_one_fifo
    #(.width_p($bits(mem_cmd_cast_i.header)))
    loopback_buffer

diff --git a/bp_top/src/v/bp_sacc_tile.sv b/bp_top/src/v/bp_sacc_tile.sv
@@ -39,11 +39,11 @@ module bp_sacc_tile
   bp_bedrock_lce_req_msg_s  cce_lce_req_li, lce_lce_req_lo;
   logic cce_lce_req_v_li, cce_lce_req_yumi_lo, lce_lce_req_v_lo, lce_req_ready_li;
   bp_bedrock_lce_cmd_msg_s cce_lce_cmd_lo, lce_lce_cmd_li;
-  logic cce_lce_cmd_v_lo, cce_lce_cmd_ready_li, lce_lce_cmd_v_li, lce_lce_cmd_yumi_lo;
+  logic cce_lce_cmd_v_lo, cce_lce_cmd_ready_and_li, lce_lce_cmd_v_li, lce_lce_cmd_yumi_lo;
   bp_bedrock_cce_mem_msg_s cce_io_cmd_lo, lce_io_cmd_li;
-  logic cce_io_cmd_v_lo, cce_io_cmd_ready_li, lce_io_cmd_v_li, lce_io_cmd_yumi_lo;
+  logic cce_io_cmd_v_lo, cce_io_cmd_ready_and_li, lce_io_cmd_v_li, lce_io_cmd_yumi_lo;
   bp_bedrock_cce_mem_msg_s cce_io_resp_li, lce_io_resp_lo;
-  logic cce_io_resp_v_li, cce_io_resp_yumi_lo, lce_io_resp_v_lo, lce_io_resp_ready_li;
+  logic cce_io_resp_v_li, cce_io_resp_yumi_lo, lce_io_resp_v_lo, lce_io_resp_ready_and_li;
 
   logic reset_r;
   always_ff @(posedge clk_i)
@@ -75,7 +75,7 @@ module bp_sacc_tile
 
      ,.io_resp_o(lce_io_resp_lo)
      ,.io_resp_v_o(lce_io_resp_v_lo)
-     ,.io_resp_ready_then_i(lce_io_resp_ready_li)
+     ,.io_resp_ready_then_i(lce_io_resp_ready_and_li)
 
      ,.lce_req_o(lce_lce_req_lo)
      ,.lce_req_v_o(lce_lce_req_v_lo)
@@ -100,11 +100,11 @@ module bp_sacc_tile
 
      ,.lce_cmd_o(cce_lce_cmd_lo)
      ,.lce_cmd_v_o(cce_lce_cmd_v_lo)
-     ,.lce_cmd_ready_then_i(cce_lce_cmd_ready_li)
+     ,.lce_cmd_ready_then_i(cce_lce_cmd_ready_and_li)
 
      ,.io_cmd_o(cce_io_cmd_lo)
      ,.io_cmd_v_o(cce_io_cmd_v_lo)
-     ,.io_cmd_ready_then_i(cce_io_cmd_ready_li)
+     ,.io_cmd_ready_then_i(cce_io_cmd_ready_and_li)
 
      ,.io_resp_i(cce_io_resp_li)
      ,.io_resp_v_i(cce_io_resp_v_li)
@@ -172,7 +172,7 @@ module bp_sacc_tile
 
      ,.packet_i(cce_lce_cmd_packet_lo)
      ,.v_i(cce_lce_cmd_v_lo)
-     ,.ready_o(cce_lce_cmd_ready_li)
+     ,.ready_o(cce_lce_cmd_ready_and_li)
 
      ,.link_i(lce_cmd_link_i)
      ,.link_o(lce_cmd_link_o)
@@ -195,7 +195,7 @@ module bp_sacc_tile
 
          ,.io_cmd_i(cce_io_cmd_lo)
          ,.io_cmd_v_i(cce_io_cmd_v_lo)
-         ,.io_cmd_ready_o(cce_io_cmd_ready_li)
+         ,.io_cmd_ready_o(cce_io_cmd_ready_and_li)
 
          ,.io_resp_o(cce_io_resp_li)
          ,.io_resp_v_o(cce_io_resp_v_li)
@@ -207,7 +207,7 @@ module bp_sacc_tile
 
          ,.io_resp_i(lce_io_resp_lo)
          ,.io_resp_v_i(lce_io_resp_v_lo)
-         ,.io_resp_ready_o(lce_io_resp_ready_li)
+         ,.io_resp_ready_o(lce_io_resp_ready_and_li)
          );
     end