Zynqparrot patches (black-parrot#900)

* Fix nbf.py * Adding INV_PARAM and AXI lite adapters * Fixing NBF * Update base address in nbf.py * Fixups * Bump CI * L2E tile fix for stream * Adding subword access capability to bedrock register module * Enabling 32-bit read of clint registers * Adding axi fifo * Adding axi fifo and unbumping CI Co-authored-by: Farzam Gilani <[email protected]>
NALAYBUDY · Jul 17, 2021 · c5cd0bc · c5cd0bc
1 parent d766c47
commit c5cd0bc
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diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -26,7 +26,6 @@ stages:
     - me_dev
     - top_dev
     - sw_dev
-    - be_dev_dcachetemptemptmep
   before_script:
       - git submodule update --init --checkout --recursive external/
   artifacts:

diff --git a/bp_be/syn/flist.vcs b/bp_be/syn/flist.vcs
@@ -242,6 +242,11 @@ $BP_ME_DIR/src/v/cce/bp_cce_src_sel.sv
 $BP_ME_DIR/src/v/cce/bp_io_cce.sv
 $BP_ME_DIR/src/v/cce/bp_cce_fsm.sv
 $BP_ME_DIR/src/v/cce/bp_cce_wrapper.sv
+# Dev
+$BP_ME_DIR/src/v/dev/bp_me_bedrock_register.sv
+$BP_ME_DIR/src/v/dev/bp_me_cfg.sv
+$BP_ME_DIR/src/v/dev/bp_me_clint_slice.sv
+$BP_ME_DIR/src/v/dev/bp_me_loopback.sv
 # Network
 $BP_ME_DIR/src/v/cce/bp_uce.sv
 $BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.sv
@@ -257,7 +262,6 @@ $BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.sv
 $BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.sv
 $BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.sv
 ## TOP
-$BP_TOP_DIR/src/v/bp_loopback.sv
 $BP_TOP_DIR/src/v/bp_nd_socket.sv
 $BP_TOP_DIR/src/v/bp_cacc_vdp.sv
 $BP_TOP_DIR/src/v/bp_cacc_tile.sv
@@ -267,10 +271,8 @@ $BP_TOP_DIR/src/v/bp_sacc_vdp.sv
 $BP_TOP_DIR/src/v/bp_sacc_tile.sv
 $BP_TOP_DIR/src/v/bp_sacc_tile_node.sv
 $BP_TOP_DIR/src/v/bp_sacc_complex.sv
-$BP_TOP_DIR/src/v/bp_cfg.sv
 $BP_TOP_DIR/src/v/bp_core.sv
 $BP_TOP_DIR/src/v/bp_core_complex.sv
-$BP_TOP_DIR/src/v/bp_clint_slice.sv
 $BP_TOP_DIR/src/v/bp_l2e_tile.sv
 $BP_TOP_DIR/src/v/bp_l2e_tile_node.sv
 $BP_TOP_DIR/src/v/bp_io_complex.sv

diff --git a/bp_common/software/py/nbf.py b/bp_common/software/py/nbf.py
@@ -75,7 +75,7 @@ class NBF:
 
   # constructor
   def __init__(self, ncpus, ucode_file, mem_file, checkpoint_file, config, skip_zeros, addr_width,
-          data_width, validate):
+          data_width, verify):
 
     # input parameters
     self.ncpus = ncpus
@@ -86,7 +86,7 @@ def __init__(self, ncpus, ucode_file, mem_file, checkpoint_file, config, skip_ze
     self.skip_zeros = skip_zeros
     self.addr_width = (addr_width+3)/4*4
     self.data_width = data_width
-    self.validate = validate
+    self.verify = verify
 
     # Grab various files
     if self.mem_file:
@@ -237,8 +237,8 @@ def dump(self):
       self.print_nbf_allcores(3, cfg_base_addr + cfg_reg_dcache_mode, 1)
       self.print_nbf_allcores(3, cfg_base_addr + cfg_reg_cce_mode, 1)
 
-      # Read back I$, D$ and CCE modes for verification
-      if self.validate:
+      if self.verify:
+        # Read back I$, D$ and CCE modes for verification
         self.print_nbf(0x12, cfg_base_addr + cfg_reg_icache_mode, 1)
         self.print_nbf(0x12, cfg_base_addr + cfg_reg_dcache_mode, 1)
         self.print_nbf(0x12, cfg_base_addr + cfg_reg_cce_mode, 1)
@@ -278,10 +278,10 @@ def dump(self):
   parser.add_argument('--skip_zeros', dest='skip_zeros', action='store_true', help='skip zero DRAM entries')
   parser.add_argument('--addr_width', type=int, default=40, help='Physical address width')
   parser.add_argument('--data_width', type=int, default=64, help='Data width')
-  parser.add_argument('--validate', dest='validate', action='store_true', help='Data width')
+  parser.add_argument("--verify", dest='verify', action='store_true', help='Read back mode registers')
 
   args = parser.parse_args()
 
   converter = NBF(args.ncpus, args.ucode_file, args.mem_file, args.checkpoint_file, args.config,
-          args.skip_zeros, args.addr_width, args.data_width, args.validate)
+          args.skip_zeros, args.addr_width, args.data_width, args.verify)
   converter.dump()
diff --git a/bp_common/src/include/bp_common_aviary_pkgdef.svh b/bp_common/src/include/bp_common_aviary_pkgdef.svh
@@ -293,7 +293,7 @@
   localparam bp_proc_param_s bp_unicore_bootrom_override_p =
     '{boot_pc        : bootrom_base_addr_gp
       ,boot_in_debug : 1
-      ,default       : "inv"
+      ,default : "inv"
       };
   `bp_aviary_derive_cfg(bp_unicore_bootrom_cfg_p
                         ,bp_unicore_bootrom_override_p

diff --git a/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh b/bp_common/src/include/bp_common_cfg_bus_pkgdef.svh
@@ -30,24 +30,24 @@
   //   16'h0800 - 16'h7fff: reserved
   //   16'h8000 - 16'h8fff: cce ucode
 
-  localparam cfg_addr_width_gp = 20;
-  localparam cfg_data_width_gp = 64;
-
-  localparam cfg_base_addr_gp          = 'h0200_0000;
-  localparam cfg_reg_unused_gp         = 'h0004;
-  localparam cfg_reg_freeze_gp         = 'h0008;
-  localparam cfg_reg_core_id_gp        = 'h000c;
-  localparam cfg_reg_did_gp            = 'h0010;
-  localparam cfg_reg_cord_gp           = 'h0014;
-  localparam cfg_reg_host_did_gp       = 'h0018;
-  localparam cfg_reg_hio_mask_gp       = 'h001c;
-  localparam cfg_reg_icache_id_gp      = 'h0200;
-  localparam cfg_reg_icache_mode_gp    = 'h0204;
-  localparam cfg_reg_dcache_id_gp      = 'h0400;
-  localparam cfg_reg_dcache_mode_gp    = 'h0404;
-  localparam cfg_reg_cce_id_gp         = 'h0600;
-  localparam cfg_reg_cce_mode_gp       = 'h0604;
-  localparam cfg_mem_base_cce_ucode_gp = 'h8000;
+  localparam cfg_base_addr_gp           = (dev_id_width_gp+dev_addr_width_gp)'('h0020_0000);
+  localparam cfg_match_addr_gp          = (dev_id_width_gp+dev_addr_width_gp)'('h002?_????);
+
+  localparam cfg_reg_unused_gp          = (dev_addr_width_gp)'('h0_0004);
+  localparam cfg_reg_freeze_gp          = (dev_addr_width_gp)'('h0_0008);
+  localparam cfg_reg_core_id_gp         = (dev_addr_width_gp)'('h0_000c);
+  localparam cfg_reg_did_gp             = (dev_addr_width_gp)'('h0_0010);
+  localparam cfg_reg_cord_gp            = (dev_addr_width_gp)'('h0_0014);
+  localparam cfg_reg_host_did_gp        = (dev_addr_width_gp)'('h0_0018);
+  localparam cfg_reg_hio_mask_gp        = (dev_addr_width_gp)'('h0_001c);
+  localparam cfg_reg_icache_id_gp       = (dev_addr_width_gp)'('h0_0200);
+  localparam cfg_reg_icache_mode_gp     = (dev_addr_width_gp)'('h0_0204);
+  localparam cfg_reg_dcache_id_gp       = (dev_addr_width_gp)'('h0_0400);
+  localparam cfg_reg_dcache_mode_gp     = (dev_addr_width_gp)'('h0_0404);
+  localparam cfg_reg_cce_id_gp          = (dev_addr_width_gp)'('h0_0600);
+  localparam cfg_reg_cce_mode_gp        = (dev_addr_width_gp)'('h0_0604);
+  localparam cfg_mem_cce_ucode_base_gp  = (dev_addr_width_gp)'('h0_8000);
+  localparam cfg_mem_cce_ucode_match_gp = (dev_addr_width_gp)'('h0_8???);
 
 `endif
 
diff --git a/bp_common/src/include/bp_common_clint_pkgdef.svh b/bp_common/src/include/bp_common_clint_pkgdef.svh
@@ -2,11 +2,19 @@
 `ifndef BP_COMMON_CLINT_PKGDEF_SVH
 `define BP_COMMON_CLINT_PKGDEF_SVH
 
-  localparam clint_base_addr_gp        = 'h0300_0000;
-  localparam mipi_reg_base_addr_gp     = 32'h0030_0000;
-  localparam mtimecmp_reg_base_addr_gp = 32'h0030_4000;
-  localparam mtime_reg_addr_gp         = 32'h0030_bff8;
-  localparam plic_reg_base_addr_gp     = 32'h0030_b000;
+
+  localparam clint_base_addr_gp         = (dev_id_width_gp+dev_addr_width_gp)'('h30_0000);
+  localparam clint_match_addr_gp        = (dev_id_width_gp+dev_addr_width_gp)'('h30_0???);
+
+  localparam mipi_reg_base_addr_gp      = dev_addr_width_gp'('h0_0000);
+  localparam mipi_reg_match_addr_gp     = dev_addr_width_gp'('h0_0???);
+
+  localparam mtimecmp_reg_base_addr_gp  = dev_addr_width_gp'('h0_4000);
+  localparam mtimecmp_reg_match_addr_gp = dev_addr_width_gp'('h0_4???);
+
+  localparam mtime_reg_addr_gp          = dev_addr_width_gp'('h0_bff8);
+  localparam mtime_reg_match_addr_gp    = dev_addr_width_gp'('h0_bff?);
+  localparam plic_reg_addr_gp           = dev_addr_width_gp'('h0_b000);
 
 `endif
 
diff --git a/bp_common/src/include/bp_common_host_pkgdef.svh b/bp_common/src/include/bp_common_host_pkgdef.svh
@@ -2,12 +2,25 @@
 `ifndef BP_COMMON_HOST_PKGDEF_SVH
 `define BP_COMMON_HOST_PKGDEF_SVH
 
-  localparam bootrom_base_addr_gp      = 32'h0001_0000;
-  localparam host_base_addr_gp         = 32'h0010_0000;
-  localparam getchar_base_addr_gp      = 32'h0010_0000;
-  localparam putchar_base_addr_gp      = 32'h0010_1000;
-  localparam finish_base_addr_gp       = 32'h0010_2000;
-  localparam putch_core_base_addr_gp   = 32'h0010_3000;
+
+  localparam host_base_addr_gp         = (dev_id_width_gp+dev_addr_width_gp)'('h0010_0000);
+  localparam host_match_addr_gp        = (dev_id_width_gp+dev_addr_width_gp)'('h001?_????);
+
+  localparam getchar_base_addr_gp      = (dev_addr_width_gp)'('h0_0000);
+  localparam getchar_match_addr_gp     = (dev_addr_width_gp)'('h0_0???);
+
+  localparam putchar_base_addr_gp      = (dev_addr_width_gp)'('h0_1000);
+  localparam putchar_match_addr_gp     = (dev_addr_width_gp)'('h0_1???);
+
+  localparam finish_base_addr_gp       = (dev_addr_width_gp)'('h0_2000);
+  localparam finish_match_addr_gp      = (dev_addr_width_gp)'('h0_2???);
+
+  localparam putch_core_base_addr_gp   = (dev_addr_width_gp)'('h0_3000);
+  localparam putch_core_match_addr_gp  = (dev_addr_width_gp)'('h0_3???);
+
+  localparam bootrom_base_addr_gp      = (dev_addr_width_gp)'('h1_0000);
+  localparam bootrom_match_addr_gp     = (dev_addr_width_gp)'('h1_????);
+
 
 `endif
 
diff --git a/bp_common/src/v/bsg_async_noc_link.sv b/bp_common/src/v/bsg_async_noc_link.sv
@@ -1,4 +1,5 @@
 
+`include "bsg_defines.v"
 `include "bsg_noc_links.vh"
 
 module bsg_async_noc_link

diff --git a/bp_common/src/v/bsg_bus_pack.sv b/bp_common/src/v/bsg_bus_pack.sv
@@ -1,4 +1,6 @@
 
+`include "bsg_defines.v"
+
 module bsg_bus_pack
  #(// Width of the entire bus
    parameter `BSG_INV_PARAM(width_p )

diff --git a/bp_common/src/v/bsg_cache_dma_to_wormhole.v b/bp_common/src/v/bsg_cache_dma_to_wormhole.v
@@ -9,20 +9,21 @@
  *          N data flits (the fill data) asynchronously.
  */
 
+`include "bsg_defines.v"
 `include "bsg_noc_links.vh"
 `include "bsg_cache.vh"
 
 module bsg_cache_dma_to_wormhole
  import bsg_noc_pkg::*;
  import bsg_cache_pkg::*;
- #(parameter dma_addr_width_p="inv" // cache addr width (byte addr)
-   , parameter dma_burst_len_p="inv" // num of data beats in dma transfer
+ #(`BSG_INV_PARAM(dma_addr_width_p) // cache addr width (byte addr)
+   , `BSG_INV_PARAM(dma_burst_len_p) // num of data beats in dma transfer
 
    // flit width should match the cache dma width.
-   , parameter wh_flit_width_p="inv"
-   , parameter wh_cid_width_p="inv"
-   , parameter wh_len_width_p="inv"
-   , parameter wh_cord_width_p="inv"
+   , `BSG_INV_PARAM(wh_flit_width_p)
+   , `BSG_INV_PARAM(wh_cid_width_p)
+   , `BSG_INV_PARAM(wh_len_width_p)
+   , `BSG_INV_PARAM(wh_cord_width_p)
 
    , parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(dma_addr_width_p)
    , parameter wh_link_sif_width_lp=`bsg_ready_and_link_sif_width(wh_flit_width_p)
@@ -301,3 +302,5 @@ module bsg_cache_dma_to_wormhole
   //synopsys translate_on
 
 endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_cache_dma_to_wormhole)
diff --git a/bp_common/src/v/bsg_dff_reset_half.v b/bp_common/src/v/bsg_dff_reset_half.v
@@ -14,7 +14,7 @@
 //
 
 module bsg_dff_reset_half
- #(parameter width_p = "inv")
+ #(`BSG_INV_PARAM(width_p ))
   (input                        clk_i
    , input                      reset_i
    , input  [width_p-1:0]       data_i
@@ -55,3 +55,5 @@ module bsg_dff_reset_half
 
 endmodule
 
+`BSG_ABSTRACT_MODULE(bsg_dff_reset_half)
+
diff --git a/bp_common/src/v/bsg_fifo_1r1w_rolly.sv b/bp_common/src/v/bsg_fifo_1r1w_rolly.sv
@@ -1,4 +1,6 @@
 
+`include "bsg_defines.v"
+
 module bsg_fifo_1r1w_rolly
   #(parameter `BSG_INV_PARAM(width_p              )
     , parameter `BSG_INV_PARAM(els_p              )

diff --git a/bp_common/src/v/bsg_parallel_in_serial_out_passthrough_dynamic.v b/bp_common/src/v/bsg_parallel_in_serial_out_passthrough_dynamic.v
@@ -24,8 +24,8 @@
 
 module bsg_parallel_in_serial_out_passthrough_dynamic
 
- #(parameter width_p       = "inv"
-  ,parameter max_els_p     = "inv"
+ #(`BSG_INV_PARAM(width_p       )
+  ,`BSG_INV_PARAM(max_els_p     )
   ,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
   )
 
@@ -160,8 +160,8 @@ module bsg_parallel_in_serial_out_passthrough_dynamic
 /*
 module bsg_parallel_in_serial_out_passthrough_dynamic
 
- #(parameter width_p       = "inv"
-  ,parameter max_els_p     = "inv"
+ #(`BSG_INV_PARAM(width_p       )
+  ,`BSG_INV_PARAM(max_els_p     )
   ,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
   )
 
@@ -251,3 +251,5 @@ module bsg_parallel_in_serial_out_passthrough_dynamic
   end
 
 endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out_passthrough_dynamic)
diff --git a/bp_common/src/v/bsg_serial_in_parallel_out_passthrough_dynamic.v b/bp_common/src/v/bsg_serial_in_parallel_out_passthrough_dynamic.v
@@ -16,8 +16,8 @@
 
 module bsg_serial_in_parallel_out_passthrough_dynamic
 
- #(parameter width_p       = "inv"
-  ,parameter max_els_p     = "inv"
+ #(`BSG_INV_PARAM(width_p       )
+  ,`BSG_INV_PARAM(max_els_p     )
   ,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
   )
 
@@ -150,3 +150,5 @@ module bsg_serial_in_parallel_out_passthrough_dynamic
   end
 
 endmodule
+
+`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_passthrough_dynamic)
diff --git a/bp_common/src/v/bsg_wormhole_stream_control.v b/bp_common/src/v/bsg_wormhole_stream_control.v
@@ -12,9 +12,12 @@
 // where (in this example) the first 2 flits are header flits and the
 //   remaining four flits are data flits
 //
+
+`include "bsg_defines.v"
+
 module bsg_wormhole_stream_control
- #(parameter len_width_p = "inv"
-   , parameter [len_width_p-1:0] hdr_len_p = "inv"
+ #(`BSG_INV_PARAM(len_width_p )
+   , `BSG_INV_PARAM([len_width_p-1:0] hdr_len_p )
    )
   (input                     clk_i
    , input                   reset_i
@@ -122,3 +125,5 @@ module bsg_wormhole_stream_control
 
 endmodule
 
+`BSG_ABSTRACT_MODULE(bsg_wormhole_stream_control)
+
diff --git a/bp_common/src/v/bsg_wormhole_stream_in.v b/bp_common/src/v/bsg_wormhole_stream_in.v
@@ -47,15 +47,15 @@ module bsg_wormhole_stream_in
    // cid_width   : the width of the concentrator id of the destination
    // Default to 0 for cord and cid, so that this module can be used either
    //   for concentrator or router
-   parameter flit_width_p      = "inv"
+   `BSG_INV_PARAM(flit_width_p      )
    , parameter cord_width_p    = 0
-   , parameter len_width_p     = "inv"
+   , `BSG_INV_PARAM(len_width_p     )
    , parameter cid_width_p     = 0
 
    // Higher level protocol information
-   , parameter pr_hdr_width_p  = "inv"
-   , parameter pr_data_width_p = "inv"
-   , parameter pr_len_width_p  = "inv"
+   , `BSG_INV_PARAM(pr_hdr_width_p  )
+   , `BSG_INV_PARAM(pr_data_width_p )
+   , `BSG_INV_PARAM(pr_len_width_p  )
 
    // Size of the wormhole header + the protocol header. The data starts afterwards.
    // Users may set this directly rather than relying on the protocol header derived default
@@ -239,3 +239,5 @@ module bsg_wormhole_stream_in
 
 endmodule
 
+`BSG_ABSTRACT_MODULE(bsg_wormhole_stream_in)
+
diff --git a/bp_common/src/v/bsg_wormhole_stream_out.v b/bp_common/src/v/bsg_wormhole_stream_out.v
@@ -42,15 +42,15 @@ module bsg_wormhole_stream_out
    // cid_width   : the width of the concentrator id of the destination
    // Default to 0 for cord and cid, so that this module can be used either
    //   for concentrator or router
-   parameter flit_width_p      = "inv"
+   `BSG_INV_PARAM(flit_width_p      )
    , parameter cord_width_p    = 0
-   , parameter len_width_p     = "inv"
+   , `BSG_INV_PARAM(len_width_p     )
    , parameter cid_width_p     = 0
 
    // Higher level protocol information
-   , parameter pr_hdr_width_p  = "inv"
-   , parameter pr_data_width_p = "inv"
-   , parameter pr_len_width_p  = "inv"
+   , `BSG_INV_PARAM(pr_hdr_width_p  )
+   , `BSG_INV_PARAM(pr_data_width_p )
+   , `BSG_INV_PARAM(pr_len_width_p  )
 
    // Size of the wormhole header + the protocol header. The data starts afterwards.
    // Users may set this directly rather than relying on the protocol header derived default
@@ -221,3 +221,5 @@ module bsg_wormhole_stream_out
 
 endmodule
 
+`BSG_ABSTRACT_MODULE(bsg_wormhole_stream_out)
+