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`timescale 1ns / 1ps | ||
////////////////////////////////////////////////////////////////////////////////// | ||
// Company: | ||
// Engineer: | ||
// | ||
// Create Date: 2017/11/02 20:49:25 | ||
// Design Name: | ||
// Module Name: ALU | ||
// Project Name: | ||
// Target Devices: | ||
// Tool Versions: | ||
// Description: | ||
// | ||
// Dependencies: | ||
// | ||
// Revision: | ||
// Revision 0.01 - File Created | ||
// Additional Comments: | ||
// | ||
////////////////////////////////////////////////////////////////////////////////// | ||
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module ALU ( | ||
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// Outputs | ||
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Result,overflow, | ||
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// Inputs | ||
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ALUCode, A, B | ||
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); | ||
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input [4:0] ALUCode; // Operation select | ||
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input [31:0] A, B; | ||
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output reg [31:0] Result; | ||
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output reg overflow; | ||
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reg signed [31:0] B_reg; | ||
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always @(B) | ||
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begin | ||
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B_reg = B; | ||
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end | ||
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// Decoded ALU operation select (ALUsel) signals | ||
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parameter alu_add= 5'b00000; | ||
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parameter alu_and= 5'b00001; | ||
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parameter alu_xor= 5'b00010; | ||
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parameter alu_or = 5'b00011; | ||
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parameter alu_nor= 5'b00100;//00100 | ||
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parameter alu_sub= 5'b00101; | ||
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parameter alu_andi= 5'b00110; | ||
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parameter alu_xori= 5'b00111; | ||
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parameter alu_ori = 5'b01000; | ||
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parameter alu_jr = 5'b01001; | ||
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parameter alu_beq= 5'b01010; | ||
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parameter alu_bne= 5'b01011; | ||
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parameter alu_bgez= 5'b01100; | ||
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parameter alu_bgtz= 5'b01101; | ||
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parameter alu_blez= 5'b01110; | ||
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parameter alu_bltz= 5'b01111; | ||
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parameter alu_sll= 5'b10000; | ||
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parameter alu_srl= 5'b10001; | ||
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parameter alu_sra= 5'b10010; | ||
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parameter alu_slt= 5'b10011; | ||
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parameter alu_sltu= 5'b10100; | ||
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parameter alu_mul= 5'b10101; | ||
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wire [31:0] sum; | ||
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wire co; | ||
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reg Binvert; //Judge add or sub | ||
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reg [31:0] B_adder; //B in adder | ||
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reg [63:0] mulre; | ||
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//Adder// | ||
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always @(*) | ||
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begin | ||
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Binvert=~(ALUCode==alu_add); | ||
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if(Binvert) | ||
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B_adder=~B+1; | ||
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else | ||
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B_adder=B; | ||
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end | ||
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adder_32bits adder_32bits_ALU( | ||
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.a(A),.b(B_adder),.ci(0),.s(sum),.co(co)); | ||
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//Result// | ||
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always @(*) | ||
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begin | ||
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case(ALUCode) | ||
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alu_add: Result=sum; | ||
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alu_and: Result=A&B; | ||
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alu_xor: Result=A^B; | ||
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alu_or: Result=A|B; | ||
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alu_nor: Result=~(A|B); | ||
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alu_sub: Result=sum; | ||
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alu_andi: Result=A&{16'b0,B[15:0]}; | ||
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alu_xori: Result=A^{16'b0,B[15:0]}; | ||
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alu_ori: Result=A|{16'b0,B[15:0]}; | ||
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alu_jr: Result=A; | ||
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alu_sll: Result=B<<A; | ||
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alu_srl: Result=B>>A; | ||
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alu_sra: Result=B_reg>>>A; | ||
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alu_slt: Result=(A[31]&&(~B[31]))||((A[31]~^B[31])&&sum[31]); | ||
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alu_sltu: Result=((~A[31])&&B[31])||((A[31]~^B[31])&&sum[31]); | ||
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default: Result=32'b0; | ||
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endcase | ||
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//judge overflow | ||
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if(co==sum[31]) | ||
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overflow=1'b1; | ||
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else | ||
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overflow=1'b0; | ||
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end | ||
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endmodule |
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