Merged with and finised eviction write buffer

eviction_write_buffer.sv

@@ -3,6 +3,8 @@ import lc3b_types::*;
 module eviction_write_buffer
 (
     input clk,
+    input ld_ewb_buff,
+    input l2_pmem_dirty_evict,
     input pmem_resp,
     input l2_pmem_read,
     input l2_pmem_write,
@@ -11,6 +13,7 @@ module eviction_write_buffer
     input lc3b_pmem_data l2_pmem_wdata,
     output lc3b_word pmem_address,
     output lc3b_pmem_data pmem_wdata,
+    output logic empty,
     output logic ready,
     output logic pmem_write
 );
@@ -21,6 +24,7 @@ logic ld_buff;
 ewb_datapath ewb_datapath
 (
     .clk(clk),
+    .ld_ewb_buff(ld_ewb_buff),
   	.l2_pmem_waddress(l2_pmem_waddress),
   	.l2_pmem_raddress(l2_pmem_raddress),
   	.l2_pmem_wdata(l2_pmem_wdata),
@@ -32,10 +36,12 @@ ewb_datapath ewb_datapath
 ewb_control ewb_control
 (
     .clk(clk),
+    .l2_pmem_dirty_evict(l2_pmem_dirty_evict),
     .l2_pmem_write(l2_pmem_write),
 	.pmem_resp(pmem_resp),
 	.ewb_addr_buff_out(ewb_addr_buff_out),
 	.l2_pmem_address(l2_pmem_raddress),
+  .empty(empty),
 	.ready(ready), 
 	.ld_buff(ld_buff), 
 	.pmem_write(pmem_write),

ewb_control.sv

@@ -4,10 +4,12 @@ module ewb_control(
     /* Input and output port declarations */
 	input clk,
 
+    input l2_pmem_dirty_evict,
 	input l2_pmem_write,
 	input pmem_resp,
 	input lc3b_word ewb_addr_buff_out,
 	input lc3b_word l2_pmem_address,
+    output logic empty,
 	output logic ready, 
 	output logic ld_buff, 
 	output logic pmem_write, 
@@ -17,12 +19,14 @@ module ewb_control(
 enum int unsigned {
     /* List of states */
     idle,
+    in_queue,
     phys_mem_write
 } state, next_state;
 
 always_comb
 begin : state_actions
     /* Default output assignments */
+    empty = 1'b0;
     ready = 1'b0;
     ld_buff = 1'b0;
     pmem_address = l2_pmem_address;
@@ -32,10 +36,16 @@ begin : state_actions
 	case(state)
     	idle: 
     	begin
+            empty = 1'b1;
     		ready = 1'b1;
-    		ld_buff = 1'b1;
     	end
 
+        in_queue: 
+        begin
+            ready = 1'b1;
+            ld_buff = 1'b1;
+        end
+
     	phys_mem_write:
     	begin
     		pmem_write = 1'b1;
@@ -56,10 +66,16 @@ begin : next_state_logic
     case(state)
     	idle: 
     	begin
-    		if (l2_pmem_write)
-    			next_state = phys_mem_write;
+    		if (l2_pmem_dirty_evict)
+    			next_state = in_queue;
     	end
 
+        in_queue: 
+        begin
+            if (l2_pmem_write)
+                next_state = phys_mem_write;
+        end
+
     	phys_mem_write:
     	begin
     		if (pmem_resp)

ewb_datapath.sv

@@ -3,6 +3,7 @@ import lc3b_types::*;
 module ewb_datapath
 (
     input clk,
+    input ld_ewb_buff,
     input lc3b_word l2_pmem_waddress,
     input lc3b_word l2_pmem_raddress,
     input lc3b_pmem_data l2_pmem_wdata,
@@ -15,16 +16,16 @@ module ewb_datapath
 register #(.width(256)) ewb_data_buff
 (
     .clk(clk),
-    .load(ld_buff),
+    .load(ld_ewb_buff),
     .in(l2_pmem_wdata),
     .out(pmem_wdata)
 );
 
 
-register #(.width(256)) ewb_addr_buff
+register #(.width(16)) ewb_addr_buff
 (
     .clk(clk),
-    .load(ld_buff),
+    .load(ld_ewb_buff),
     .in(l2_pmem_waddress),
     .out(ewb_addr_buff_out)
 );

l2_cache.sv

@@ -3,6 +3,7 @@ import lc3b_types::*;
 module l2_cache
 (
     input clk,
+    input ewb_empty,
     input ewb_ready,
     input mem_read,
     input mem_write,
@@ -17,7 +18,9 @@ module l2_cache
     output lc3b_mem_data mem_rdata,
     output lc3b_word pmem_address,
     output lc3b_word pmem_waddress,
-    output lc3b_pmem_data pmem_wdata
+    output lc3b_pmem_data pmem_wdata,
+    output logic l2_pmem_dirty_evict,
+    output logic ld_ewb_buff
 );
 
 logic ld_cache;
@@ -75,6 +78,7 @@ l2_cache_datapath l2_cache_datapath
 l2_cache_control l2_cache_control
 (
     .clk(clk),
+    .ewb_empty(ewb_empty),
     .ewb_ready(ewb_ready),
     .hit(hit),
     .curr_way(curr_way),
@@ -104,7 +108,9 @@ l2_cache_control l2_cache_control
     .pmem_waddress(pmem_waddress),
     .mem_resp(mem_resp),
     .pmem_read(pmem_read),
-    .pmem_write(pmem_write)
+    .pmem_write(pmem_write), 
+    .l2_pmem_dirty_evict(l2_pmem_dirty_evict),
+    .ld_ewb_buff(ld_ewb_buff)
 );
 
 endmodule : l2_cache

l2_cache_control.sv

@@ -8,6 +8,7 @@ module l2_cache_control
     input clk,
 
     /* Datapath signals */
+    input ewb_empty,
     input ewb_ready, 
     input hit,
     input [1:0] curr_way,
@@ -39,7 +40,9 @@ module l2_cache_control
     output lc3b_word pmem_waddress,
     output logic mem_resp,
     output logic pmem_read,
-    output logic pmem_write
+    output logic pmem_write,
+	 output logic l2_pmem_dirty_evict,
+     output logic ld_ewb_buff
 );
 
 
@@ -73,6 +76,8 @@ begin: state_actions
     pmem_write = 1'b0;
     pmem_address = mem_address;
 	 pmem_waddress = mem_address;
+     l2_pmem_dirty_evict = 1'b0;
+     ld_ewb_buff = 1'b0;
 
     /* Actions for each state */
     case (state)
@@ -146,6 +151,10 @@ begin: state_actions
 
             pmem_waddress = {pmem_tag, mem_address[8:5], 5'b00000};
             ld_cache = 1'b1;
+            l2_pmem_dirty_evict = 1'b1;
+            if (ewb_empty)
+                ld_ewb_buff = 1'b1;
+
             if (ewb_ready)
                 pmem_read = 1'b1;
 

modules/register_neg.sv

@@ -0,0 +1,35 @@
+/*
+ * Register module (provided)
+ */
+module register_neg #(parameter width = 16)
+(
+    input clk,
+    input load,
+    input [width-1:0] in,
+    output logic [width-1:0] out
+);
+
+logic [width-1:0] data;
+
+/* Altera device registers are 0 at power on. Specify this
+ * so that Modelsim works as expected.
+ */
+initial
+begin
+    data = 1'b0;
+end
+
+always_ff @(negedge clk)
+begin
+    if (load)
+    begin
+        data = in;
+    end
+end
+
+always_comb
+begin
+    out = data;
+end
+
+endmodule : register_neg

mp3.qpf

@@ -18,12 +18,20 @@
 #
 # Quartus II 32-bit
 # Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+<<<<<<< HEAD
 # Date created = 04:28:40  December 06, 2015
+=======
+# Date created = 03:53:51  December 06, 2015
+>>>>>>> 7b5f9c358e37683ba827fab6e2781b0b16014535
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "13.1"
+<<<<<<< HEAD
 DATE = "04:28:40  December 06, 2015"
+=======
+DATE = "03:53:51  December 06, 2015"
+>>>>>>> 7b5f9c358e37683ba827fab6e2781b0b16014535
 
 # Revisions
 

mp3.sv

@@ -101,6 +101,9 @@ logic l2_pmem_write;
 lc3b_word pmem_waddress;
 lc3b_word pmem_raddress;
 lc3b_pmem_data l2_pmem_wdata;
+logic l2_pmem_dirty_evict;
+logic ewb_empty;
+logic ld_ewb_buff;
 
 /* Instantiate MP 3 top level blocks here */
 datapath datapath_module
@@ -192,6 +195,7 @@ victim_cache victim_cache
 l2_cache l2_cache
 (
     .clk(clk),
+    .ewb_empty(ewb_empty),
     .ewb_ready(ewb_ready),
     .mem_read(l2_mem_read),
     .mem_write(l2_mem_write),
@@ -206,13 +210,17 @@ l2_cache l2_cache
     .mem_rdata(l2_mem_rdata_in),
     .pmem_address(pmem_raddress),
     .pmem_waddress(pmem_waddress),
-    .pmem_wdata(l2_pmem_wdata)
+    .pmem_wdata(l2_pmem_wdata),
+    .l2_pmem_dirty_evict(l2_pmem_dirty_evict),
+    .ld_ewb_buff(ld_ewb_buff)
 
 );
 
 eviction_write_buffer eviction_write_buffer
 (
     .clk(clk),
+    .ld_ewb_buff(ld_ewb_buff),
+    .l2_pmem_dirty_evict(l2_pmem_dirty_evict),
     .pmem_resp(pmem_resp),
     .l2_pmem_read(pmem_read),
     .l2_pmem_write(l2_pmem_write),
@@ -221,6 +229,7 @@ eviction_write_buffer eviction_write_buffer
     .l2_pmem_wdata(l2_pmem_wdata),
     .pmem_address(pmem_address),
     .pmem_wdata(pmem_wdata),
+    .empty(ewb_empty),
     .ready(ewb_ready),
     .pmem_write(pmem_write)
 );

mp3_nativelink_simulation.rpt

@@ -121,6 +121,30 @@ ModelSim-Altera Info: # -- Compiling module arbiter_control
 ModelSim-Altera Info: # 
 ModelSim-Altera Info: # Top level modules:
 ModelSim-Altera Info: # 	arbiter_control
+ModelSim-Altera Info: # vlog -sv -work work +incdir+/home/mychen5/ece411/JZ-Wentworth-Cache-Now {/home/mychen5/ece411/JZ-Wentworth-Cache-Now/ewb_datapath.sv}
+ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+ModelSim-Altera Info: # -- Compiling package ewb_datapath_sv_unit
+ModelSim-Altera Info: # -- Importing package lc3b_types
+ModelSim-Altera Info: # -- Compiling module ewb_datapath
+ModelSim-Altera Info: # 
+ModelSim-Altera Info: # Top level modules:
+ModelSim-Altera Info: # 	ewb_datapath
+ModelSim-Altera Info: # vlog -sv -work work +incdir+/home/mychen5/ece411/JZ-Wentworth-Cache-Now {/home/mychen5/ece411/JZ-Wentworth-Cache-Now/ewb_control.sv}
+ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+ModelSim-Altera Info: # -- Compiling package ewb_control_sv_unit
+ModelSim-Altera Info: # -- Importing package lc3b_types
+ModelSim-Altera Info: # -- Compiling module ewb_control
+ModelSim-Altera Info: # 
+ModelSim-Altera Info: # Top level modules:
+ModelSim-Altera Info: # 	ewb_control
+ModelSim-Altera Info: # vlog -sv -work work +incdir+/home/mychen5/ece411/JZ-Wentworth-Cache-Now {/home/mychen5/ece411/JZ-Wentworth-Cache-Now/eviction_write_buffer.sv}
+ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+ModelSim-Altera Info: # -- Compiling package eviction_write_buffer_sv_unit
+ModelSim-Altera Info: # -- Importing package lc3b_types
+ModelSim-Altera Info: # -- Compiling module eviction_write_buffer
+ModelSim-Altera Info: # 
+ModelSim-Altera Info: # Top level modules:
+ModelSim-Altera Info: # 	eviction_write_buffer
 ModelSim-Altera Info: # vlog -sv -work work +incdir+/home/mychen5/ece411/JZ-Wentworth-Cache-Now/modules {/home/mychen5/ece411/JZ-Wentworth-Cache-Now/modules/zext.sv}
 ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
 ModelSim-Altera Info: # -- Compiling package zext_sv_unit
@@ -519,6 +543,12 @@ ModelSim-Altera Info: # Loading work.pseudo_lru_sv_unit
 ModelSim-Altera Info: # Loading work.pseudo_lru
 ModelSim-Altera Info: # Loading work.l2_cache_control_sv_unit
 ModelSim-Altera Info: # Loading work.l2_cache_control
+ModelSim-Altera Info: # Loading work.eviction_write_buffer_sv_unit
+ModelSim-Altera Info: # Loading work.eviction_write_buffer
+ModelSim-Altera Info: # Loading work.ewb_datapath_sv_unit
+ModelSim-Altera Info: # Loading work.ewb_datapath
+ModelSim-Altera Info: # Loading work.ewb_control_sv_unit
+ModelSim-Altera Info: # Loading work.ewb_control
 ModelSim-Altera Info: # Loading work.arbiter_sv_unit
 ModelSim-Altera Info: # Loading work.arbiter
 ModelSim-Altera Info: # Loading work.arbiter_datapath_sv_unit