Implemented LC3X; Not Tested; conv_tool unfinished;

control_rom.sv

@@ -2,6 +2,7 @@ import lc3b_types::*;
 module control_rom
 (
     input lc3b_opcode opcode,
+    input lc3b_lc3x lc3x_check,
     input imm_enable,
     input jsr_enable,
     input d_enable,
@@ -47,28 +48,58 @@ begin
         case(opcode)
             op_add:
             begin
-                ctrl.aluop = alu_add;
-                ctrl.load_regfile = 1'b1;
-                ctrl.load_cc = 1'b1;
-                if (imm_enable == 1'b1)
+                if (lc3x_check == 2'b00)            //addition
+                begin
+                    ctrl.aluop = alu_add;
+                    if (imm_enable == 1'b1)
+                    begin
+                        /* DR <= A & SEXT(IR[4:0]) */
+                        ctrl.alumux_sel = 2'b10;
+                        ctrl.imm_enable = 1'b1;
+                    end
+                end
+                /*LC-3X instructions do not need immediate*/
+                else if (lc3x_check == 2'b01)       //division
+                begin
+                    ctrl.aluop = alu_div;
+                end
+
+                else if (lc3x_check == 2'b10)       //multiplication
+                begin
+                    ctrl.aluop = alu_mult;
+                end
+
+                else if (lc3x_check == 2'b11)       //subtraction
                 begin
-                    /* DR <= A & SEXT(IR[4:0]) */
-                    ctrl.alumux_sel = 2'b10;
-                    ctrl.imm_enable = 1'b1;
+                    ctrl.aluop = alu_sub;
                 end
+                ctrl.load_regfile = 1'b1;
+                ctrl.load_cc = 1'b1;        
             end
 
             op_and:
             begin
-                ctrl.aluop = alu_and;
-                ctrl.load_regfile = 1'b1;
-                ctrl.load_cc = 1'b1;
-                if (imm_enable == 1'b1)
+                if (lc3x_check == 2'b00)            //AND
+                    ctrl.aluop = alu_and;
+                    if (imm_enable == 1'b1)
+                    begin
+                        /* DR <= A & SEXT(IR[4:0]) */
+                        ctrl.alumux_sel = 2'b10;
+                        ctrl.imm_enable = 1'b1;
+                    end
+                end
+                else if (lc3x_check == 2'b01)       //OR
+                begin
+                    ctrl.aluop = alu_or;
+                end
+
+                else if (lc3x_check == 2'b10)       //XOR
                 begin
-                    /* DR <= A & SEXT(IR[4:0]) */
-                    ctrl.alumux_sel = 2'b10;
-                    ctrl.imm_enable = 1'b1;
+                    ctrl.aluop = alu_xor;
                 end
+                ctrl.load_regfile = 1'b1;
+                ctrl.load_cc = 1'b1;
+
             end
 
             op_not:

datapath.sv

@@ -59,6 +59,7 @@ lc3b_offset6 offset6;
 lc3b_byte trapvect8;
 lc3b_offset9 offset9;
 lc3b_offset11 offset11;
+lc3b_lc3x lc3x_check;
 
 lc3b_word zext4_out;
 lc3b_word sext5_out;
@@ -235,6 +236,7 @@ ir ir_module
     .trapvect8(trapvect8),
     .offset9(offset9),
     .offset11(offset11),
+    .lc3x_check(lc3x_check),
     .d_enable(d_enable),
     .imm_enable(imm_enable),
     .jsr_enable(jsr_enable),
@@ -249,6 +251,7 @@ ir ir_module
 control_rom control_rom_module
 (
     .opcode(opcode),
+    .lc3x_check(lc3x_check),
     .imm_enable(imm_enable),
     .jsr_enable(jsr_enable),
     .d_enable(d_enable),

lc3b_types.sv

@@ -14,6 +14,7 @@ typedef logic [5:0] lc3b_offset6;
 typedef logic [4:0] lc3b_offset5;
 typedef logic [3:0] lc3b_offset4;
 typedef logic [2:0] lc3b_offset3;
+typedef logic [2:0] lc3b_lc3x;
 
 typedef logic [2:0] lc3b_reg;
 typedef logic [2:0] lc3b_nzp;
@@ -28,7 +29,12 @@ typedef logic [8:0] lc3b_c_tag;
 
 typedef enum bit [3:0] {
     op_add  = 4'b0001,
+    //  op_div = 4'b0001            bits [4:3] = 01
+    //  op_mult = 4'b0001                      = 10
+    //  op_sub = 4'b0001                       = 11
     op_and  = 4'b0101,
+    //  op_or = 4'b0101                        = 01
+    //  op_xor = 4'b0101                       = 10
     op_br   = 4'b0000,
     op_jmp  = 4'b1100,   /* also RET */
     op_jsr  = 4'b0100,   /* also JSRR */
@@ -47,7 +53,12 @@ typedef enum bit [3:0] {
 
 typedef enum bit [3:0] {
     alu_add,
+    alu_sub,
+    alu_mult,
+    alu_div,
     alu_and,
+    alu_or,
+    alu_xor,
     alu_not,
     alu_pass,
     alu_sll,

lc3x_conv_tool.py

@@ -0,0 +1,52 @@
+# The goal of this tool is to convert a lc3x asm file to a lc3b asm file.
+# Instructions necessary to remove in conversion are  DIV, MULT, SUB, XOR, and OR  
+# Instructions look like this (for split reference): SUB dest, R1, R2
+
+import logging
+import argparse
+
+def clean(self, filename):
+	with open(filename) as f_old, open('converted_' + filename,'w') as f_new:
+		for line in f_old:
+			instr_whole = line.split()
+			instruction = instr_whole[0]
+			regs = instr_whole[1:]
+			# get only the number of the register
+			dest = ((regs[0])[:-1])[1]
+			R1 = ((regs[1])[:-1])[1]
+			R2 = (regs[2])[1]
+			# removing div
+			binary_dest = '{0:03b}'.format(int(dest))
+			binary_R1 = '{0:03b}'.format(int(R1))
+			binary_R2 = '{0:03b}'.format(int(R2))
+			if instruction == 'DIV':
+				concat = (binary_dest << 11) + (binary_R1 << 8) + bin(0) + '01' + str(binary_R2)
+				f_new.write('DATA 4x1'+'')
+
+			elif instruction == 'MULT':
+
+
+			elif instruction == 'SUB':
+
+
+			elif instruction == 'XOR':
+
+
+			elif instruction == 'OR':
+
+
+			else:
+				f_new.write(line)
+		f_new.close()
+
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('filename', help='Determine which asm file to use (include ".asm" on input)')
+    args = parser.parse_args()
+    clean(args.filename)
+
+
+
+if __name__ == '__main__':
+    main()

modules/alu.sv

@@ -12,7 +12,12 @@ always_comb
 begin
     case (aluop)
         alu_add: f = a + b;
+        alu_sub: f = a - b;
+        alu_mult: f = a * b;
+        alu_div: f = a / b;         //division is really bad in circuits because of high complexity and high cycles
         alu_and: f = a & b;
+        alu_or: f = a | b;
+        alu_xor: f = a ^ b;
         alu_not: f = ~a;
         alu_pass: f = a;
         alu_sll: f = a << b;

modules/ir.sv

@@ -17,6 +17,7 @@ module ir
     output lc3b_byte trapvect8,
     output lc3b_offset9 offset9,
     output lc3b_offset11 offset11,
+    output lc3b_lc3x lc3x_check,
     output logic d_enable,
     output logic imm_enable,
     output logic jsr_enable,
@@ -57,6 +58,7 @@ begin
     d_enable   = data[4];
     imm_enable = data[5];
     jsr_enable = data[11];
+    lc3x_check = data[4:3]
     out = data;
 end