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CMO Extension, cbo.zero instruction details #4240

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plutsyk opened this issue Jan 27, 2025 · 2 comments
Closed
5 tasks done

CMO Extension, cbo.zero instruction details #4240

plutsyk opened this issue Jan 27, 2025 · 2 comments
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@plutsyk
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plutsyk commented Jan 27, 2025

Before start

  • I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
  • I have read the XiangShan Documents. 我已经阅读过香山文档。
  • I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
  • I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
  • I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

It seems that implementation of the cbo.zero instruction would require updates to few other places in the code base, analogous to those made at StoreQueueData.scala#L78. For instance, in case of LoadQueueRAW.scala#L287, it would require checks whether "querying" stores (in io.storeIn) are coming from the cbo.zero instruction, i.e. writing the entire cache lines or not. Currently such checks seem to be missing, which strongly suggests possible issues for memory model correctness... unless this is taken care of elsewhere in the design. Perhaps you could provide a bit of clarification or hints in the latter case.
@plutsyk plutsyk added the question Question requiring answer label Jan 27, 2025
@Anzooooo
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Yes, this does present a certain problem, thank you for pointing this out and we will address this issue subsequently.

@Anzooooo Anzooooo self-assigned this Feb 13, 2025
@Anzooooo Anzooooo mentioned this issue Feb 16, 2025
Merged
Tang-Haojin pushed a commit that referenced this issue Feb 17, 2025
@Anzooooo @linjuanZ
fix(LSU): fix cbo instr exceptions and implementation (#4262)
3c808de 
1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:#4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>
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The issue has now been resolved by the pr mentioned, thanks for pointing it out.

ChrisYzcc pushed a commit to ChrisYzcc/XiangShan that referenced this issue Feb 22, 2025
@Anzooooo @linjuanZ @ChrisYzcc
fix(LSU): fix cbo instr exceptions and implementation (OpenXiangShan#…
1a0a777 
…4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:OpenXiangShan#4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>
ChrisYzcc pushed a commit to ChrisYzcc/XiangShan that referenced this issue Feb 22, 2025
@Anzooooo @linjuanZ @ChrisYzcc
fix(LSU): fix cbo instr exceptions and implementation (OpenXiangShan#…
f4e19dd 
…4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:OpenXiangShan#4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>
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