Basic bitserial implementation -- addi, lui, shifts, branches need work

Former-commit-id: f0a945c

bp_be/src/include/bp_be_bserial_pkg.vh

@@ -0,0 +1,23 @@
+
+package bp_be_bserial_pkg;
+
+  typedef enum bit[3:0]
+  {
+    e_bserial_op_add     = 4'b0000
+    , e_bserial_op_sub   = 4'b1000
+    , e_bserial_op_sll   = 4'b0001
+    , e_bserial_op_slt   = 4'b0010
+    , e_bserial_op_xor   = 4'b0100
+    , e_bserial_op_and   = 4'b0111
+    , e_bserial_op_or    = 4'b0110
+    , e_bserial_op_sext  = 4'b1001
+    , e_bserial_op_eq    = 4'b1100
+    , e_bserial_op_ne    = 4'b1110
+    , e_bserial_op_passb = 4'b1111
+  } bp_be_bserial_opcode_e;
+
+  `define bp_be_bserial_opcode_width \
+    ($bits(bp_be_bserial_opcode_e))
+
+endpackage : bp_be_bserial_pkg
+

bp_be/src/v/bp_be_bserial/bp_be_bserial_adder.v

@@ -0,0 +1,34 @@
+/*
+ * bp_be_bserial_adder.v
+ *
+ * Notes: DOES NOT HANDLE OVERFLOW.  We'll probably need to have an exception be raised...if we
+ *          care.  Benchmarks probably don't test this :)
+ */ 
+
+
+module bp_be_bserial_adder
+  (input                         clk_i
+   , input                       clr_i
+
+   , input                       a_i
+   , input                       b_i
+   , output                      s_o
+   );
+
+logic c_r, c_n;
+
+assign s_o = a_i ^ b_i ^ c_r;
+assign c_n = (a_i & b_i) | (b_i & c_r) | (a_i & c_r);
+
+always_ff @(posedge clk_i)
+  begin
+    if (clr_i)
+        c_r <= 1'b0;
+    else 
+      begin
+        c_r <= c_n;
+      end
+  end
+
+endmodule : bp_be_bserial_adder
+

bp_be/src/v/bp_be_bserial/bp_be_bserial_alu.v

@@ -1,56 +1,117 @@
 
 module bp_be_bserial_alu
- #(localparam opcode_width_lp = 4)
-  (input                         a_i
+ import bp_be_rv64_pkg::*;
+ import bp_be_bserial_pkg::*;
+ #(localparam opcode_width_lp  = `bp_be_bserial_opcode_width
+
+   , localparam reg_data_width_lp = rv64_reg_data_width_gp)
+  (input                         clk_i
+   , input                       reset_i 
+
+   , input                       clr_i
+   , input                       set_i
+
+   , input                       a_i
    , input                       b_i
-   , input                       c_i
 
    , input [opcode_width_lp-1:0] op_i
 
    , output                      s_o
-   , output                      c_o
    );
 
+// Casting
+bp_be_bserial_opcode_e op;
+logic c_n, c_r;
+logic s, s_r;
+
+assign op  = bp_be_bserial_opcode_e'(op_i);
+assign s_o = s;
+
 always_comb 
   begin
-    unique case (op_i)
-      e_bserial_add: 
+    unique case (op)
+      e_bserial_op_add: 
+        begin
+          s = a_i ^ b_i ^ c_r;
+          c_n = (a_i & b_i) | (b_i & c_r) | (a_i & c_r);
+        end
+
+      e_bserial_op_sub:
+        begin
+          s = a_i ^ ~b_i ^ c_r;
+          c_n = (a_i & ~b_i) | (~b_i & c_r) | (a_i & c_r);
+        end
+
+      e_bserial_op_sll:
+        begin
+          s = 1'b0;
+          c_n = '0;
+        end
+
+      e_bserial_op_sext:
+        begin
+          s = s_r;
+          c_n = 1'b0;
+        end
+
+      e_bserial_op_ne:
         begin
-          s_o = a_i ^ b_i ^ c_i;
-          c_o = (a_i & b_i) | (b_i & c_i) | (a_i & c_i);
+          s   = c_r | (a_i != b_i);
+          c_n = c_r | (a_i != b_i);
         end
 
-      e_bserial_and:
+      e_bserial_op_eq:
         begin
-          s_o = a_i & b_i;
-          c_o = 1'b0;
+          s   = ~(c_r | (a_i != b_i));
+          c_n =   c_r | (a_i != b_i); 
         end
 
-      e_bserial_or:
+      e_bserial_op_and:
         begin
-          s_o = a_i | b_i;
-          c_o = 1'b0;
+          s = a_i & b_i;
+          c_n = 1'b0;
         end
 
-      e_bserial_xor:
+      e_bserial_op_or:
         begin
-          s_o = a_i ^ b_i;
-          c_o = 1'b0;
+          s = a_i | b_i;
+          c_n = 1'b0;
         end
 
-      e_bserial_sltu:
+      e_bserial_op_xor:
         begin
-          s_o = (~a_i & b_i) | c_i;
-          c_o = c_i;
+          s = a_i ^ b_i;
+          c_n = 1'b0;
+        end
+
+      e_bserial_op_passb:
+        begin
+          s = b_i;
+          c_n = 1'b0;
         end
 
       default:
         begin
-          s_o = 1'b0;
-          c_o = 1'b0;
+          $display("ERROR: op %s not currently supported", op);
+          s = 1'b0;
+          c_n = 1'b0;
         end
     endcase
   end
 
+always_ff @(posedge clk_i)
+  begin
+    if (reset_i | set_i | clr_i)
+      begin
+        c_r <= set_i & ~clr_i & ~reset_i;
+        s_r <= 1'b0;
+      end
+    else 
+      begin
+        c_r <= c_n;
+        s_r <= s;
+      end
+  end
+
 endmodule : bp_be_bserial_alu