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cvfpu Public
Forked from openhwgroup/cvfpuParametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
SystemVerilog Apache License 2.0 UpdatedSep 12, 2024 -
embench-iot Public
Forked from embench/embench-iotThe main Embench repository
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cheshire Public
Forked from pulp-platform/cheshireA minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Verilog Other UpdatedSep 5, 2024 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Assembly Other UpdatedFeb 20, 2024 -
culsans Public
Forked from pulp-platform/culsansTightly-coupled cache coherence unit for CVA6 using the ACE protocol
C UpdatedJan 19, 2024 -
cva6_perf_analysis Public
Scritps to run and analyze performance on CVA6
Python UpdatedApr 21, 2022 -
black-parrot Public
Forked from black-parrot/black-parrotA Linux-capable host multicore for and by the world
SystemVerilog BSD 3-Clause "New" or "Revised" License UpdatedMar 9, 2021 -
core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedFeb 16, 2021 -
pulp Public
Forked from pulp-platform/pulpThis is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
SystemVerilog Other UpdatedFeb 11, 2021 -
cv32e40p Public
Forked from openhwgroup/cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog Other UpdatedApr 21, 2020