Skip to content

Commit

Permalink
Add and fix some tests for PPC64
Browse files Browse the repository at this point in the history
Summary:
TestExprsChar.py
Char is unsigned char by default in PowerPC.

TestDisassembleBreakpoint.py
Modify disassemble testcase to consider multiple architectures.

TestThreadJump.py
Jumping directly to the return line on PowerPC architecture dos not
means returning the value that is seen on the code. The last test fails,
because it needs the execution of some assembly in the beginning of the
function. Avoiding this test for this architecture.

TestEhFrameUnwind.py
Implement func for ppc64le test case.

TestWatchLocation.py
TestStepOverWatchpoint.py
PowerPC currently supports only one H/W watchpoint.

TestDisassembleRawData.py
Add PowerPC opcode and instruction for disassemble testcase.

Reviewers: labath

Reviewed By: labath

Subscribers: davide, labath, alexandreyy, lldb-commits, luporl, lbianc

Differential Revision: https://reviews.llvm.org/D44472
Patch by Alexandre Yukio Yamashita <[email protected]>.

git-svn-id: https://llvm.org/svn/llvm-project/lldb/trunk@328488 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information
labath committed Mar 26, 2018
1 parent b13323d commit 6b0a122
Show file tree
Hide file tree
Showing 6 changed files with 37 additions and 35 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,7 @@ def test_default_char(self):
archs=[
"arm",
"aarch64",
"powerpc64le",
"s390x"],
bugnumber="llvm.org/pr23069")
@expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr21765")
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,9 @@ def test(self):
self.expect("file " + exe,
patterns=["Current executable set to .*a.out.*"])

self.runCmd("dis -n main")
disassembly_before_break = self.res.GetOutput().splitlines()

match_object = lldbutil.run_break_set_command(self, "br s -n sum")
lldbutil.check_breakpoint_result(
self,
Expand All @@ -37,36 +40,16 @@ def test(self):
self.expect("run",
patterns=["Process .* launched: "])

self.runCmd("dis -f")
disassembly = self.res.GetOutput()

# ARCH, if not specified, defaults to x86_64.
arch = self.getArchitecture()
if arch in ["", 'x86_64', 'i386', 'i686']:
breakpoint_opcodes = ["int3"]
instructions = [' mov', ' addl ', 'ret']
elif arch in ["arm", "aarch64", "arm64", "armv7", "armv7k"]:
breakpoint_opcodes = ["brk", "udf"]
instructions = [' add ', ' ldr ', ' str ']
elif re.match("mips", arch):
breakpoint_opcodes = ["break"]
instructions = ['lw', 'sw']
elif arch in ["s390x"]:
breakpoint_opcodes = [".long"]
instructions = [' l ', ' a ', ' st ']
else:
# TODO please add your arch here
self.fail(
'unimplemented for arch = "{arch}"'.format(
arch=self.getArchitecture()))
self.runCmd("dis -n main")
disassembly_after_break = self.res.GetOutput().splitlines()

# make sure that the software breakpoint has been removed
for op in breakpoint_opcodes:
self.assertFalse(op in disassembly)
# make sure all assembly instructions are the same as the original
# instructions before inserting breakpoints.
self.assertEqual(len(disassembly_before_break),
len(disassembly_after_break))

# make sure a few reasonable assembly instructions are here
self.expect(
disassembly,
exe=False,
startstr="a.out`sum",
substrs=instructions)
for dis_inst_before, dis_inst_after in \
zip(disassembly_before_break, disassembly_after_break):
inst_before = dis_inst_before.split(':')[-1]
inst_after = dis_inst_after.split(':')[-1]
self.assertEqual(inst_before, inst_after)
Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
void func() {

#ifndef __mips__
#ifdef __powerpc64__
__asm__ (
"mflr 0;"
"std 0,16(1);"
"addi 1,1,-24;"
"mr 31,1;"
".cfi_def_cfa_offset 24;"
"addi 0,0,0;"
"addi 1,1,24;"
"ld 0,16(1);"
".cfi_def_cfa_offset 0;"
);
#elif !defined __mips__
__asm__ (
"pushq $0x10;"
".cfi_def_cfa_offset 16;"
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,8 @@ def setUp(self):
# Most of the MIPS boards provide only one H/W watchpoints, and S/W
# watchpoints are not supported yet
@expectedFailureAll(triple=re.compile('^mips'))
# SystemZ also currently supports only one H/W watchpoint
@expectedFailureAll(archs=['s390x'])
# SystemZ and PowerPC also currently supports only one H/W watchpoint
@expectedFailureAll(archs=['powerpc64le', 's390x'])
@skipIfDarwin
def test_hello_watchlocation(self):
"""Test watching a location with '-s size' option."""
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ def test(self):
# Most of the MIPS boards provide only one H/W watchpoints, and S/W
# watchpoints are not supported yet
arch = self.getArchitecture()
if re.match("^mips", arch):
if re.match("^mips", arch) or re.match("powerpc64le", arch):
self.runCmd("watchpoint delete 1")

# resolve_location=True, read=False, write=True
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,9 @@ def test_disassemble_raw_data(self):
elif re.match("mips", arch):
target = self.dbg.CreateTargetWithFileAndTargetTriple("", "mips")
raw_bytes = bytearray([0x03, 0xa0, 0xf0, 0x21])
elif re.match("powerpc64le", arch):
target = self.dbg.CreateTargetWithFileAndTargetTriple("", "powerpc64le")
raw_bytes = bytearray([0x00, 0x00, 0x80, 0x38])
else:
target = self.dbg.CreateTargetWithFileAndTargetTriple("", "x86_64")
raw_bytes = bytearray([0x48, 0x89, 0xe5])
Expand All @@ -48,6 +51,9 @@ def test_disassemble_raw_data(self):
self.assertTrue(inst.GetMnemonic(target) == "move")
self.assertTrue(inst.GetOperands(target) ==
'$' + "fp, " + '$' + "sp")
elif re.match("powerpc64le", arch):
self.assertTrue(inst.GetMnemonic(target) == "li")
self.assertTrue(inst.GetOperands(target) == "4, 0")
else:
self.assertTrue(inst.GetMnemonic(target) == "movq")
self.assertTrue(inst.GetOperands(target) ==
Expand Down

0 comments on commit 6b0a122

Please sign in to comment.