Pa1mantri
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RISC-V_HDP Public
Design of a Customizable RISC-V SoC for Clapswitch Application
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VSD_MEMSOC Public
Caravel intergration of VSDMEMSOC design
Verilog Apache License 2.0 UpdatedJun 12, 2024 -
tt07_cdc_fifo Public
"Clock Domain Crossing FIFO" Tapedout using TInytapeout(tt07) shuttle
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VSD_Hardware_Design Public
Pre and Post Synthesis Simulation of a Design VSDMemSOC
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CellDesign Public
Adding a Customized Standard Cell into the OpenLane Flow
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VSDMemSOC Public
VSDMemSOC Implementation flow:: RTL2GDSII
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RISC-V_Core_Myth Public
riscv-myth-workshop-sep23-Pa1mantri created by GitHub Classroom
TL-Verilog UpdatedSep 29, 2023