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- Renamed RTL_v1.8.0 to RTL_v1.8.0.
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- Updated links due to 1 level up index.html.
- Added links to additional documents and reports.

Signed-off-by: Pascal Gouedo <[email protected]>
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Pascal Gouedo committed Jun 19, 2024
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88 changes: 51 additions & 37 deletions Project-Descriptions-and-Plans/CV32E40Pv2/Milestone-data/RTL_v1.8.3/index.html
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<head>
<meta charset="utf-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<img src="img/openhw-landscape.svg">
<img src="Reports/img/openhw-landscape.svg">
<title>CORE-V-VERIF Documentation Home</title>
<h1>Documentation for CORE-V verification</h1>
<p>The place to start is the <a href="https://docs.openhwgroup.org/projects/core-v-verif/en/latest/quick_start.html">CORE-V Verification Strategy</a>.</p>
<p><b>Simulation verification</b> methodology used for all CORE-V cores is described in following document: <a href="https://docs.openhwgroup.org/projects/core-v-verif/en/latest/quick_start.html">CORE-V Verification Strategy</a></p>
<p>For CV32E40Pv2, <b>RISC-V ISA Formal Verification</b> methodology was used and is described <a href="https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_RISCV_vPlan_v1.1.pdf">here</a>.</p>
<p>Documentation for the various CORE-V cores are maintained in <a href="https://github.com/openhwgroup/core-v-docs">core-v-docs</a>, the OpenHW Group's CORE-V documentation repo.</p>
<p></p>
<p>As much as is practical, we try to add documentation where you actually use it. Most directories in this repository will have a <b>README.md</b> and GitHub
will automatically render it into something readable. So, if you want to "dive right in", start with the README at the top of this repo and go from there.
If that does not answer you question(s), please do raise an issue.</p>
<p>As much as is practical, we try to add documentation where you actually use it.<br>
Most directories in this repository will have a <b>README.md</b> and GitHub
will automatically render it into something readable.<br>
So, if you want to "dive right in", start with the README at the top of this repo and go from there.<br>
If that does not answer you question(s), please do raise an issue.</p>
</head>

<br><br>
<br>

<!-- <body style="background-color:powderblue;"> -->
<h2>CV32E40P v1.8.0 database</h2>
<p>Database for the cv32e40p_v1.8.0 release.</p>
<h2>CV32E40P v1.8.3 database</h2>
<p>Database for the cv32e40p_v1.8.3 release.</p>
<ul>
<li>RTL git repository: <a href="https://github.com/openhwgroup/cv32e40p">cv32e40p</a> <mark> TODO: provide v1.8.0 TAG link instead. </mark></li>
<li>Verification git repository: <a href="https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/release">core-v-verif</a> <mark> TODO: provide v1.8.0 TAG link instead. </mark></li>
<li>Embecosm Toolchain: <a href="https://www.embecosm.com/resources/tool-chain-downloads/#corev">CORE-V top-of-tree compilers for CentOS 7 (corev-openhw-gcc-centos7-20240407)</a></li>
<li>Imperas DV / Reference Model: eng.20240501.0</li>
<li>RTL git repository: <a href="https://github.com/openhwgroup/cv32e40p">cv32e40p</a> <mark> TODO: provide v1.8.3 TAG link instead. </mark></li>
<li>Verification git repository: <a href="https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/release">core-v-verif</a> <mark> TODO: provide v1.8.3 TAG link instead. </mark></li>
<li>Embecosm Toolchain: <a href="https://www.embecosm.com/resources/tool-chain-downloads/#corev">corev-openhw-gcc-centos7-20240530</a></li>
<li>Synopsys Imperas Reference Model: eng.20240530.0</li>
</ul>

<br><br>
<br>

<h2>CV32E40P v1.8.0 RISCOF Reports</h2>
<h2>CV32E40P v1.8.3 RISCOF Reports</h2>
<ul>
<li>CFG_P: <a href="RISCOF/CFG_P/report.html">CFG_P RISC Report</a></li>
<li>CFG_P_F0: <a href="RISCOF/CFG_P_F0/report.html">CFG_P_F0 RISC Report</a></li>
<li>CFG_P_F1: <a href="RISCOF/CFG_P_F1/report.html">CFG_P_F1 RISC Report</a></li>
<li>CFG_P_F2: <a href="RISCOF/CFG_P_F2/report.html">CFG_P_F2 RISC Report</a></li>
<li>CFG_P: <a href="Reports/RISCOF/CFG_P/report.html">CFG_P RISC Report</a></li>
<li>CFG_P_F0: <a href="Reports/RISCOF/CFG_P_F0/report.html">CFG_P_F0 RISC Report</a></li>
<li>CFG_P_F1: <a href="Reports/RISCOF/CFG_P_F1/report.html">CFG_P_F1 RISC Report</a></li>
<li>CFG_P_F2: <a href="Reports/RISCOF/CFG_P_F2/report.html">CFG_P_F2 RISC Report</a></li>
</ul>

<br><br>
<br>

<h2>CV32E40P v1.8.0 Verifiction Plan(s) (aka Test Plans)</h2>
<p>DVPlans could be found in core-v-verif git repositories <a href="https://github.com/openhwgroup/core-v-verif/tree/72660aea6c528c986886e90692317bb0849373d9/cv32e40p/docs/VerifPlans/Simulation">VerifPlans</a></p>

<br><br>

<h2>CV32E40P v1.8.0 Simulation Results</h2>
<p>1. Results for the cv32e40p_v1.8.0 release.</p>
<h2>CV32E40P v1.8.3 Verification Plan(s) (aka Test Plans)</h2>
<p>Main verification methodology was through the use of RISC-V ISA Formal Verification where all RISC-V standard and custom extension (XPULP) instructions are formally verified against Sail models.<br>
A tool was then used to generate assertion for each of these instructions additionally to OBI interfaces assertions and to some pipeline assetions.</p>
<p>Then Simulation verification was used to verify what can't be modelized and verified using Formal, like Hardware Loops, Prefetch and Fetch pipeline stages...</p>
<ul>
<p>This is the result presented at Cores Task Group meeting on 2024-05-06: </p>
<ul><li>Jump to RTL Code Coverage & Functional Coverage results <a href="Coverage/index.html">here</a></li></ul>
<ul><li>Jump to Simulation regression results <a href="Simulation/index.html">here</a></li></ul>
<ul><li>Jump to riscvISACOV results <a href="riscvISACOV/htmlcovreport/index.html">here</a></li></ul>
<ul><li>Jump to riscvISA Formal (OneSpin) results <a href="Formal/index.html">here</a></li></ul>
<li>RISC-V ISA Formal Verification Plan:<br>
The formal verification plan (excel file) could be found <a href="https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal">here</a>.<br>
</li>
<li>Simulation Verification Plans:<br>
Overall description of simulation verification plans can be found <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/README.md">here</a>.<br>
All the DVPlans could be found in core-v-verif git repositories <a href="https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation">Simulation</a>.<br>
A file listing all the tests is available <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/CV32E40Pv2_test_list.xlsx">here</a>.
</li>
<br>
</ul>
<p>2. Final RTL freeze v2.0.0</p>

<br>

<h2>CV32E40P v1.8.3 Verification Results</h2>
<p>Results for the cv32e40p_v1.8.3 release:</p>
<ul>
<p><mark>TODO</mark></p>
<li>RISC-V ISA Formal verification results are <a href="Reports/RISC-V_ISA_Formal/Property_Status-v1_8_0.xlsx">here</a>.</li>
<li>Simulation regression results are <a href="Reports/Simulation/index.html">here</a>.</li>
<li>RTL Code Coverage & Functional Coverage results are <a href="Reports/Coverage/index.html">here</a>.</li>
<li>riscvISACOV results are available either in <a href="Reports/riscvISACOV/htmlcovreport/index.html">html</a> or in <a href="Reports/riscvISACOV/textcovreport">text</a> reports.<br>
For the text reports, there are either complete or only showing covergroups and coverpoints holes (i.e. not having 100% coverage).</li>
<li>All RTL issues found either with RISC-V ISA Formal or Simulation are listed <a href="CV32E40Pv2_Design_Issue_Summary.xlsx">here</a>.</li>
<li>Known regression failures are analyzed and documented <a href="CV32E40Pv2_regression_known_failure.xlsx">here</a>.</li>
<li>Uncovered RTL Code Coverage are analyzed and documented <a href="CV32E40Pv2_uncovered_coverage_explanation.xlsx">here</a>.</li>
<li>All the waivers applied are documented <a href="CV32E40Pv2_waiver_list.xlsx">here</a>.</li>

</ul>

<br><br>
<br>

<h2>Declarations</h2>
<p>1) Full test suites and verifications are executed on 7 configurations listed below. </p>
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</ul>
<p>2) COREV_CLUSTER configuration is not verified. </p>
<p>3) ci_check are run and all v1 legacy tests are run also in v2 regression. They were enhanced to be v1 and v2 compliant tests.</p>
<p>4) All the waivers applied are documented in this excel. <mark> Link: TODO </mark> </p>
<p>5) Uncovered RTL Code Coverage are analyzed and documented in this excel (core-v-verif issues filed). <mark> Link: TODO </mark> </p>
<p>6) Known regression failures are analyzed and documented in this excel (core-v-verif issues filed). <mark> Link: TODO </mark> </p>

</body>

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