Coarse Grained Reconfigurable Array

Basic Verilog Ethernet core and C driver functions

Implementation for MatMul-free LM.

Get up and running with Llama 3.3, DeepSeek-R1, Phi-4, Gemma 2, and other large language models.

iCESugar series FPGA dev board

Verilog AXI components for FPGA implementation

SERV - The SErial RISC-V CPU

Ethernet MAC 10/100 Mbps

Nix Packages collection & NixOS

System-on-Chip for In-Silicon Verification of IP Cores

Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores

Running Linux on IOb-SoC-OpenCryptoHW

UART 16550 core

RISC-V System on Chip Template

A FPGA friendly 32 bit RISC-V CPU implementation