First SystemVerilog example in the Chisel book

chisel-book.tex

@@ -3977,7 +3977,7 @@ \section{A Light Flasher Example}
 and \emph{off}; the second FSM to count the remaining flashes.
 Listing~\ref{lst:counter:fsm} code shows the down counter FSM:
 
-\verylonglist{code/flasher2_counter.txt}{The down counter FAM.}{lst:counter:fsm}
+\verylonglist{code/flasher2_counter.txt}{The down counter FSM.}{lst:counter:fsm}
 
 
 \noindent Note that the counter is loaded with 2 for 3 flashes, as it counts the
@@ -6081,7 +6081,7 @@ \section{Simulator Backends}
 \myref{https://www.veripool.org/wiki/verilator}{Verilator} and
 \myref{https://www.synopsys.com/verification/simulation/vcs.html}{Synopsys VCS}. Because
 Verilator is open-source, we will use it for the examples presented in this section. Note
-that in all cases, VCS can be be used as an alternative to Verilator.
+that in all cases, VCS can be used as an alternative to Verilator.
 
 Switching to a different backend is simply a matter of adding another annotation to the
 \code{withAnnotations} call as shown in the Waveforms section. To use Verilator, add the following
@@ -6924,6 +6924,10 @@ \section*{Source Access}
 
 \appendix
 
+\chapter{SystemVerilog and VHDL}
+
+\longlist{code/sv_first.txt}{First SystemVerilog example in the Chisel book}{lst:sv:first}
+
 \chapter{Reserved Keywords}
 \index{Reserved keywords}
 \label{sec:reserved}

slides/05_testing.tex

@@ -15,6 +15,14 @@
 \titlepage
 \end{frame}
 
+\begin{frame}[fragile]{TODO 2024}
+\begin{itemize}
+\item This is material for barely one hour -- extend it
+\item Testing needs a for loop: explain it and some Scala (in the testing context)
+\item Maybe a better test example. At least make it a 4 Mux and write when it is done, same for the Heap example
+\end{itemize}
+\end{frame}
+
 \begin{frame}[fragile]{Overview}
 \begin{itemize}
 \item Today is Open House

src/main/scala/verilog/Simple.scala

@@ -0,0 +1,38 @@
+package verilog
+
+import chisel3._
+import chisel3.util._
+class Simple extends BlackBox with HasBlackBoxInline {
+  val io = IO(new Bundle() {
+    val a, b = Input(UInt(8.W))
+    val c = Output(UInt(8.W))
+  })
+
+  setInline("Simple.sv",
+    """module Simple(
+          input  [7:0] a,
+          input  [7:0] b,
+          output reg [7:0] c
+      );
+//- start sv_first
+always_comb begin
+  c = a + b;
+end
+//- end
+      endmodule
+  """)
+}
+
+class SimpleTop extends Module {
+  val io = IO(new Bundle() {
+    val a, b = Input(UInt(8.W))
+    val c = Output(UInt(8.W))
+  })
+
+  val m = Module(new Simple)
+  m.io <> io
+}
+
+object Simple extends App {
+  println(getVerilogString(new SimpleTop()))
+}

src/test/scala/verilog/SimpleTest.scala

@@ -0,0 +1,16 @@
+package verilog
+
+import chisel3._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+class SimpleTest extends AnyFlatSpec with ChiselScalatestTester {
+  "Simple" should "pass" in {
+    test(new SimpleTop()).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut =>
+      dut.io.a.poke(1.U)
+      dut.io.b.poke(3.U)
+      dut.clock.step()
+      dut.io.c.expect(4.U)
+    }
+  }
+}