Test VHDL example

QISAIYINANA · Sep 18, 2023 · 7bec7e7 · 7bec7e7
1 parent 395399e
commit 7bec7e7
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Showing 3 changed files with 11 additions and 10 deletions.
diff --git a/Makefile b/Makefile
@@ -8,6 +8,9 @@ all: test gencode fig book genslides
 test:
 	sbt test
 
+vhdl:
+	make -C src/main/vhdl
+
 gencode:
 	-mkdir code
 	sbt -Dsbt.main.class=sbt.ScriptMain scripts/gencode.scala
@@ -44,12 +47,6 @@ clean:
 	rm -rf target
 	rm -rf generated
 
-chisel:
-	sbt "runMain Snippets"
-	sbt "runMain Counter"
-	sbt "test:runMain RegisterTester"
-	sbt "test:runMain LogicTester"
-
 # test only one
 flasher:
 	sbt "testOnly FlasherSpec"

diff --git a/src/main/vhdl/Makefile b/src/main/vhdl/Makefile
@@ -0,0 +1,7 @@
+
+# Run VHDL tests
+
+all:
+	ghdl -a basic.vhdl
+	ghdl -e adder_tb
+	ghdl -r adder_tb
diff --git a/src/main/vhdl/basic.vhdl b/src/main/vhdl/basic.vhdl
@@ -68,9 +68,6 @@ begin
     wait for 10 ns;
     assert sum = "11111110" report "255 + 255 = 510" severity note;
 
-    a <= "11111111";
-    b <= "11111111";
-    wait for 10 ns;
-    assert sum = "11111111" report "255 + 255 = 510" severity note;
+    wait;
 end process;
 end architecture;