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[MachineScheduler] checkResourceLimit boundary condition update
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When we call checkResourceLimit in bumpCycle or bumpNode, and we
know the resource count has just reached the limit (the equations
 are equal). We should return true to mark that we are resource
limited for next schedule, or else we might continue to schedule
in favor of latency for 1 more schedule and create a schedule that
 actually overbook the resource.

When we call checkResourceLimit to estimate the resource limite before
scheduling, we don't need to return true even if the equations are
equal, as it shouldn't limit the schedule for it .

Differential Revision: https://reviews.llvm.org/D62345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362805 91177308-0d34-0410-b5e6-96231b3b80d8
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Jinsong Ji committed Jun 7, 2019
1 parent 226232f commit 40b689d
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Showing 6 changed files with 33 additions and 27 deletions.
16 changes: 11 additions & 5 deletions lib/CodeGen/MachineScheduler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1837,9 +1837,15 @@ SchedBoundary::~SchedBoundary() { delete HazardRec; }

/// Given a Count of resource usage and a Latency value, return true if a
/// SchedBoundary becomes resource limited.
/// If we are checking after scheduling a node, we should return true when
/// we just reach the resource limit.
static bool checkResourceLimit(unsigned LFactor, unsigned Count,
unsigned Latency) {
return (int)(Count - (Latency * LFactor)) > (int)LFactor;
unsigned Latency, bool AfterSchedNode) {
int ResCntFactor = (int)(Count - (Latency * LFactor));
if (AfterSchedNode)
return ResCntFactor >= (int)LFactor;
else
return ResCntFactor > (int)LFactor;
}

void SchedBoundary::reset() {
Expand Down Expand Up @@ -2134,7 +2140,7 @@ void SchedBoundary::bumpCycle(unsigned NextCycle) {
CheckPending = true;
IsResourceLimited =
checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
getScheduledLatency());
getScheduledLatency(), true);

LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName()
<< '\n');
Expand Down Expand Up @@ -2302,7 +2308,7 @@ void SchedBoundary::bumpNode(SUnit *SU) {
// resource limited. If a stall occurred, bumpCycle does this.
IsResourceLimited =
checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
getScheduledLatency());
getScheduledLatency(), true);

// Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
// resets CurrMOps. Loop to handle instructions with more MOps than issue in
Expand Down Expand Up @@ -2521,7 +2527,7 @@ void GenericSchedulerBase::setPolicy(CandPolicy &Policy, bool IsPostRA,
RemLatency = computeRemLatency(CurrZone);
RemLatencyComputed = true;
OtherResLimited = checkResourceLimit(SchedModel->getLatencyFactor(),
OtherCount, RemLatency);
OtherCount, RemLatency, false);
}

// Schedule aggressively for latency in PostRA mode. We don't check for
Expand Down
4 changes: 2 additions & 2 deletions test/CodeGen/PowerPC/build-vector-tests.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2024,8 +2024,8 @@ define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) {
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfd f0, 24(r3)
; P9LE-NEXT: lfd f2, 8(r3)
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: xxmrghd vs0, vs2, vs0
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: lfd f3, 0(r3)
; P9LE-NEXT: xvcvdpsxws v2, vs0
; P9LE-NEXT: xxmrghd vs0, vs3, vs1
Expand Down Expand Up @@ -3608,8 +3608,8 @@ define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) {
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfd f0, 24(r3)
; P9LE-NEXT: lfd f2, 8(r3)
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: xxmrghd vs0, vs2, vs0
; P9LE-NEXT: lfd f1, 16(r3)
; P9LE-NEXT: lfd f3, 0(r3)
; P9LE-NEXT: xvcvdpuxws v2, vs0
; P9LE-NEXT: xxmrghd vs0, vs3, vs1
Expand Down
6 changes: 3 additions & 3 deletions test/CodeGen/PowerPC/csr-save-restore-order.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,9 +57,9 @@ define i64 @test(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
; CHECK-PWR9-NEXT: .cfi_offset v31, -304
; CHECK-PWR9-NEXT: std r14, 240(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r15, 248(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r16, 256(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v20, 48(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v21, 64(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: std r16, 256(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v22, 80(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: std r17, 264(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v23, 96(r1) # 16-byte Folded Spill
Expand Down Expand Up @@ -112,8 +112,8 @@ define i64 @test(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
; CHECK-PWR9-NEXT: ld r4, 32(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: add r3, r4, r3
; CHECK-PWR9-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v27, 160(r1) # 16-byte Folded Reload
; CHECK-PWR9-NEXT: lxv v26, 144(r1) # 16-byte Folded Reload
Expand All @@ -128,11 +128,11 @@ define i64 @test(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
; CHECK-PWR9-NEXT: lfd f29, 504(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f28, 496(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f27, 488(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f26, 480(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r31, 376(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r30, 368(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r29, 360(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r28, 352(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f26, 480(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r27, 344(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r26, 336(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r25, 328(r1) # 8-byte Folded Reload
Expand Down
2 changes: 1 addition & 1 deletion test/CodeGen/PowerPC/f128-passByValue.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,7 @@ define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-LABEL: maxVecParam:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
; CHECK-NEXT: xsaddqp v2, v2, v4
; CHECK-NEXT: xsaddqp v2, v2, v5
; CHECK-NEXT: xsaddqp v2, v2, v6
Expand All @@ -95,7 +96,6 @@ define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
; CHECK-NEXT: xsaddqp v2, v2, v11
; CHECK-NEXT: xsaddqp v2, v2, v12
; CHECK-NEXT: xsaddqp v2, v2, v13
; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
; CHECK-NEXT: xssubqp v2, v2, v[[REG0]]
; CHECK-NEXT: blr
fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
Expand Down
16 changes: 8 additions & 8 deletions test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -167,15 +167,15 @@ define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x dou
; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs6, 16(r4)
; CHECK-P9-NEXT: lxv vs7, 0(r4)
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
Expand All @@ -195,15 +195,15 @@ define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x dou
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
Expand Down Expand Up @@ -381,15 +381,15 @@ define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <1
; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: lxv vs3, 64(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3
; CHECK-P9-NEXT: lxv vs4, 48(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
; CHECK-P9-NEXT: lxv vs5, 32(r4)
; CHECK-P9-NEXT: lxv vs6, 16(r4)
; CHECK-P9-NEXT: lxv vs7, 0(r4)
; CHECK-P9-NEXT: xvcvdpsxds vs7, vs7
; CHECK-P9-NEXT: xvcvdpsxds vs6, vs6
; CHECK-P9-NEXT: xvcvdpsxds vs5, vs5
; CHECK-P9-NEXT: xvcvdpsxds vs3, vs3
; CHECK-P9-NEXT: xvcvdpsxds vs4, vs4
; CHECK-P9-NEXT: xvcvdpsxds vs2, vs2
; CHECK-P9-NEXT: xvcvdpsxds vs1, vs1
; CHECK-P9-NEXT: xvcvdpsxds vs0, vs0
Expand All @@ -409,15 +409,15 @@ define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <1
; CHECK-BE-NEXT: lxv vs1, 96(r4)
; CHECK-BE-NEXT: lxv vs2, 80(r4)
; CHECK-BE-NEXT: lxv vs3, 64(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3
; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4
; CHECK-BE-NEXT: lxv vs5, 32(r4)
; CHECK-BE-NEXT: lxv vs6, 16(r4)
; CHECK-BE-NEXT: lxv vs7, 0(r4)
; CHECK-BE-NEXT: xvcvdpsxds vs7, vs7
; CHECK-BE-NEXT: xvcvdpsxds vs6, vs6
; CHECK-BE-NEXT: xvcvdpsxds vs5, vs5
; CHECK-BE-NEXT: xvcvdpsxds vs3, vs3
; CHECK-BE-NEXT: xvcvdpsxds vs4, vs4
; CHECK-BE-NEXT: xvcvdpsxds vs2, vs2
; CHECK-BE-NEXT: xvcvdpsxds vs1, vs1
; CHECK-BE-NEXT: xvcvdpsxds vs0, vs0
Expand Down
16 changes: 8 additions & 8 deletions test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -167,15 +167,15 @@ define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x
; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: xvcvuxddp vs4, v5
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: xvcvuxddp vs3, v0
; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvuxddp vs0, v7
; CHECK-P9-NEXT: xvcvuxddp vs1, v6
; CHECK-P9-NEXT: xvcvuxddp vs2, v1
; CHECK-P9-NEXT: xvcvuxddp vs4, v5
; CHECK-P9-NEXT: xvcvuxddp vs3, v0
; CHECK-P9-NEXT: xvcvuxddp vs5, v4
; CHECK-P9-NEXT: xvcvuxddp vs6, v3
; CHECK-P9-NEXT: xvcvuxddp vs7, v2
Expand All @@ -195,15 +195,15 @@ define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x
; CHECK-BE-NEXT: lxv v3, 96(r4)
; CHECK-BE-NEXT: lxv v4, 80(r4)
; CHECK-BE-NEXT: lxv v5, 64(r4)
; CHECK-BE-NEXT: xvcvuxddp vs4, v5
; CHECK-BE-NEXT: lxv v0, 48(r4)
; CHECK-BE-NEXT: xvcvuxddp vs3, v0
; CHECK-BE-NEXT: lxv v1, 32(r4)
; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: lxv v7, 0(r4)
; CHECK-BE-NEXT: xvcvuxddp vs0, v7
; CHECK-BE-NEXT: xvcvuxddp vs1, v6
; CHECK-BE-NEXT: xvcvuxddp vs2, v1
; CHECK-BE-NEXT: xvcvuxddp vs4, v5
; CHECK-BE-NEXT: xvcvuxddp vs3, v0
; CHECK-BE-NEXT: xvcvuxddp vs5, v4
; CHECK-BE-NEXT: xvcvuxddp vs6, v3
; CHECK-BE-NEXT: xvcvuxddp vs7, v2
Expand Down Expand Up @@ -381,15 +381,15 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result,
; CHECK-P9-NEXT: lxv v3, 96(r4)
; CHECK-P9-NEXT: lxv v4, 80(r4)
; CHECK-P9-NEXT: lxv v5, 64(r4)
; CHECK-P9-NEXT: xvcvsxddp vs4, v5
; CHECK-P9-NEXT: lxv v0, 48(r4)
; CHECK-P9-NEXT: xvcvsxddp vs3, v0
; CHECK-P9-NEXT: lxv v1, 32(r4)
; CHECK-P9-NEXT: lxv v6, 16(r4)
; CHECK-P9-NEXT: lxv v7, 0(r4)
; CHECK-P9-NEXT: xvcvsxddp vs0, v7
; CHECK-P9-NEXT: xvcvsxddp vs1, v6
; CHECK-P9-NEXT: xvcvsxddp vs2, v1
; CHECK-P9-NEXT: xvcvsxddp vs4, v5
; CHECK-P9-NEXT: xvcvsxddp vs3, v0
; CHECK-P9-NEXT: xvcvsxddp vs5, v4
; CHECK-P9-NEXT: xvcvsxddp vs6, v3
; CHECK-P9-NEXT: xvcvsxddp vs7, v2
Expand All @@ -409,15 +409,15 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result,
; CHECK-BE-NEXT: lxv v3, 96(r4)
; CHECK-BE-NEXT: lxv v4, 80(r4)
; CHECK-BE-NEXT: lxv v5, 64(r4)
; CHECK-BE-NEXT: xvcvsxddp vs4, v5
; CHECK-BE-NEXT: lxv v0, 48(r4)
; CHECK-BE-NEXT: xvcvsxddp vs3, v0
; CHECK-BE-NEXT: lxv v1, 32(r4)
; CHECK-BE-NEXT: lxv v6, 16(r4)
; CHECK-BE-NEXT: lxv v7, 0(r4)
; CHECK-BE-NEXT: xvcvsxddp vs0, v7
; CHECK-BE-NEXT: xvcvsxddp vs1, v6
; CHECK-BE-NEXT: xvcvsxddp vs2, v1
; CHECK-BE-NEXT: xvcvsxddp vs4, v5
; CHECK-BE-NEXT: xvcvsxddp vs3, v0
; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: xvcvsxddp vs7, v2
Expand Down

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