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Remove the mblaze backend from llvm.
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Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187145 91177308-0d34-0410-b5e6-96231b3b80d8
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@espindola
espindola committed Jul 25, 2013
1 parent bef4c3e commit 6fccaaf
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1 change: 0 additions & 1 deletion CMakeLists.txt
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Expand Up @@ -79,7 +79,6 @@ set(LLVM_ALL_TARGETS
CppBackend
Hexagon
Mips
MBlaze
MSP430
NVPTX
PowerPC
Expand Down
7 changes: 1 addition & 6 deletions autoconf/configure.ac
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Expand Up @@ -407,7 +407,6 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
xcore-*) llvm_cv_target_arch="XCore" ;;
msp430-*) llvm_cv_target_arch="MSP430" ;;
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
nvptx-*) llvm_cv_target_arch="NVPTX" ;;
s390x-*) llvm_cv_target_arch="SystemZ" ;;
*) llvm_cv_target_arch="Unknown" ;;
Expand Down Expand Up @@ -442,7 +441,6 @@ case $host in
xcore-*) host_arch="XCore" ;;
msp430-*) host_arch="MSP430" ;;
hexagon-*) host_arch="Hexagon" ;;
mblaze-*) host_arch="MBlaze" ;;
s390x-*) host_arch="SystemZ" ;;
*) host_arch="Unknown" ;;
esac
Expand Down Expand Up @@ -674,7 +672,6 @@ else
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
MSP430) AC_SUBST(TARGET_HAS_JIT,0) ;;
Hexagon) AC_SUBST(TARGET_HAS_JIT,0) ;;
MBlaze) AC_SUBST(TARGET_HAS_JIT,0) ;;
NVPTX) AC_SUBST(TARGET_HAS_JIT,0) ;;
SystemZ) AC_SUBST(TARGET_HAS_JIT,1) ;;
*) AC_SUBST(TARGET_HAS_JIT,0) ;;
Expand Down Expand Up @@ -824,7 +821,7 @@ if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon SystemZ R600" ;;
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Expand All @@ -841,7 +838,6 @@ case "$enableval" in
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
systemz) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
r600) TARGETS_TO_BUILD="R600 $TARGETS_TO_BUILD" ;;
Expand All @@ -853,7 +849,6 @@ case "$enableval" in
AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
Expand Down
10 changes: 2 additions & 8 deletions configure
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Expand Up @@ -4033,7 +4033,6 @@ else
xcore-*) llvm_cv_target_arch="XCore" ;;
msp430-*) llvm_cv_target_arch="MSP430" ;;
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
nvptx-*) llvm_cv_target_arch="NVPTX" ;;
s390x-*) llvm_cv_target_arch="SystemZ" ;;
*) llvm_cv_target_arch="Unknown" ;;
Expand Down Expand Up @@ -4068,7 +4067,6 @@ case $host in
xcore-*) host_arch="XCore" ;;
msp430-*) host_arch="MSP430" ;;
hexagon-*) host_arch="Hexagon" ;;
mblaze-*) host_arch="MBlaze" ;;
s390x-*) host_arch="SystemZ" ;;
*) host_arch="Unknown" ;;
esac
Expand Down Expand Up @@ -5424,8 +5422,6 @@ else
MSP430) TARGET_HAS_JIT=0
;;
Hexagon) TARGET_HAS_JIT=0
;;
MBlaze) TARGET_HAS_JIT=0
;;
NVPTX) TARGET_HAS_JIT=0
;;
Expand Down Expand Up @@ -5664,7 +5660,7 @@ if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon SystemZ R600" ;;
all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Expand All @@ -5681,7 +5677,6 @@ case "$enableval" in
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
systemz) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;;
r600) TARGETS_TO_BUILD="R600 $TARGETS_TO_BUILD" ;;
Expand All @@ -5693,7 +5688,6 @@ case "$enableval" in
AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
Expand Down Expand Up @@ -10551,7 +10545,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
#line 10554 "configure"
#line 10548 "configure"
#include "confdefs.h"

#if HAVE_DLFCN_H
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9 changes: 0 additions & 9 deletions docs/CodeGenerator.rst
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Expand Up @@ -1788,7 +1788,6 @@ Here is the table:
:raw-html:`<th>Feature</th>`
:raw-html:`<th>ARM</th>`
:raw-html:`<th>Hexagon</th>`
:raw-html:`<th>MBlaze</th>`
:raw-html:`<th>MSP430</th>`
:raw-html:`<th>Mips</th>`
:raw-html:`<th>NVPTX</th>`
Expand All @@ -1803,7 +1802,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_reliable">is generally reliable</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
:raw-html:`<td class="yes"></td> <!-- Mips -->`
:raw-html:`<td class="yes"></td> <!-- NVPTX -->`
Expand All @@ -1818,7 +1816,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_asmparser">assembly parser</a></td>`
:raw-html:`<td class="no"></td> <!-- ARM -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
:raw-html:`<td class="no"></td> <!-- Mips -->`
:raw-html:`<td class="no"></td> <!-- NVPTX -->`
Expand All @@ -1833,7 +1830,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_disassembler">disassembler</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
:raw-html:`<td class="no"></td> <!-- Mips -->`
:raw-html:`<td class="na"></td> <!-- NVPTX -->`
Expand All @@ -1848,7 +1844,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_inlineasm">inline asm</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
:raw-html:`<td class="no"></td> <!-- Mips -->`
:raw-html:`<td class="yes"></td> <!-- NVPTX -->`
Expand All @@ -1863,7 +1858,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_jit">jit</a></td>`
:raw-html:`<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
:raw-html:`<td class="yes"></td> <!-- Mips -->`
:raw-html:`<td class="na"></td> <!-- NVPTX -->`
Expand All @@ -1878,7 +1872,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>`
:raw-html:`<td class="no"></td> <!-- ARM -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
:raw-html:`<td class="no"></td> <!-- Mips -->`
:raw-html:`<td class="na"></td> <!-- NVPTX -->`
Expand All @@ -1893,7 +1886,6 @@ Here is the table:
:raw-html:`<td><a hr:raw-html:`ef="#feat_tailcall">tail calls</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
:raw-html:`<td class="no"></td> <!-- Mips -->`
:raw-html:`<td class="no"></td> <!-- NVPTX -->`
Expand All @@ -1908,7 +1900,6 @@ Here is the table:
:raw-html:`<td><a href="#feat_segstacks">segmented stacks</a></td>`
:raw-html:`<td class="no"></td> <!-- ARM -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
:raw-html:`<td class="no"></td> <!-- Mips -->`
:raw-html:`<td class="no"></td> <!-- NVPTX -->`
Expand Down
2 changes: 1 addition & 1 deletion docs/GettingStarted.rst
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Expand Up @@ -758,7 +758,7 @@ The following options can be used to set or enable LLVM specific options:
target names that you want available in llc. The target names use all lower
case. The current set of targets is:

``arm, cpp, hexagon, mblaze, mips, mipsel, msp430, powerpc, ptx, sparc, spu,
``arm, cpp, hexagon, mips, mipsel, msp430, powerpc, ptx, sparc, spu,
systemz, x86, x86_64, xcore``.

``--enable-doxygen``
Expand Down
1 change: 0 additions & 1 deletion include/llvm/ADT/Triple.h
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Expand Up @@ -64,7 +64,6 @@ class Triple {
x86, // X86: i[3-9]86
x86_64, // X86-64: amd64, x86_64
xcore, // XCore: xcore
mblaze, // MBlaze: mblaze
nvptx, // NVPTX: 32-bit
nvptx64, // NVPTX: 64-bit
le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
Expand Down
7 changes: 0 additions & 7 deletions include/llvm/IR/CallingConv.h
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Expand Up @@ -93,13 +93,6 @@ namespace CallingConv {
/// Passes all arguments in register or parameter space.
PTX_Device = 72,

/// MBLAZE_INTR - Calling convention used for MBlaze interrupt routines.
MBLAZE_INTR = 73,

/// MBLAZE_INTR - Calling convention used for MBlaze interrupt support
/// routines (i.e. GCC's save_volatiles attribute).
MBLAZE_SVOL = 74,

/// SPIR_FUNC - Calling convention for SPIR non-kernel device functions.
/// No lowering or expansion of arguments.
/// Structures are passed as a pointer to a struct with the byval attribute.
Expand Down
30 changes: 1 addition & 29 deletions include/llvm/Support/ELF.h
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Expand Up @@ -276,7 +276,6 @@ enum {
EM_STM8 = 186, // STMicroeletronics STM8 8-bit microcontroller
EM_TILE64 = 187, // Tilera TILE64 multicore architecture family
EM_TILEPRO = 188, // Tilera TILEPro multicore architecture family
EM_MICROBLAZE = 189, // Xilinx MicroBlaze 32-bit RISC soft processor core
EM_CUDA = 190, // NVIDIA CUDA architecture
EM_TILEGX = 191, // Tilera TILE-Gx multicore architecture family
EM_CLOUDSHIELD = 192, // CloudShield architecture family
Expand All @@ -287,8 +286,7 @@ enum {
EM_RL78 = 197, // Renesas RL78 family
EM_VIDEOCORE5 = 198, // Broadcom VideoCore V processor
EM_78KOR = 199, // Renesas 78KOR family
EM_56800EX = 200, // Freescale 56800EX Digital Signal Controller (DSC)
EM_MBLAZE = 47787 // Xilinx MicroBlaze
EM_56800EX = 200 // Freescale 56800EX Digital Signal Controller (DSC)
};

// Object file classes.
Expand Down Expand Up @@ -418,32 +416,6 @@ enum {
R_386_NUM = 43
};

// MBlaze relocations.
enum {
R_MICROBLAZE_NONE = 0,
R_MICROBLAZE_32 = 1,
R_MICROBLAZE_32_PCREL = 2,
R_MICROBLAZE_64_PCREL = 3,
R_MICROBLAZE_32_PCREL_LO = 4,
R_MICROBLAZE_64 = 5,
R_MICROBLAZE_32_LO = 6,
R_MICROBLAZE_SRO32 = 7,
R_MICROBLAZE_SRW32 = 8,
R_MICROBLAZE_64_NONE = 9,
R_MICROBLAZE_32_SYM_OP_SYM = 10,
R_MICROBLAZE_GNU_VTINHERIT = 11,
R_MICROBLAZE_GNU_VTENTRY = 12,
R_MICROBLAZE_GOTPC_64 = 13,
R_MICROBLAZE_GOT_64 = 14,
R_MICROBLAZE_PLT_64 = 15,
R_MICROBLAZE_REL = 16,
R_MICROBLAZE_JUMP_SLOT = 17,
R_MICROBLAZE_GLOB_DAT = 18,
R_MICROBLAZE_GOTOFF_64 = 19,
R_MICROBLAZE_GOTOFF_32 = 20,
R_MICROBLAZE_COPY = 21
};

// ELF Relocation types for PPC32
enum {
R_PPC_NONE = 0, /* No relocation. */
Expand Down
2 changes: 0 additions & 2 deletions lib/Object/ELFYAML.cpp
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Expand Up @@ -176,7 +176,6 @@ ScalarEnumerationTraits<ELFYAML::ELF_EM>::enumeration(IO &IO,
ECase(EM_STM8)
ECase(EM_TILE64)
ECase(EM_TILEPRO)
ECase(EM_MICROBLAZE)
ECase(EM_CUDA)
ECase(EM_TILEGX)
ECase(EM_CLOUDSHIELD)
Expand All @@ -188,7 +187,6 @@ ScalarEnumerationTraits<ELFYAML::ELF_EM>::enumeration(IO &IO,
ECase(EM_VIDEOCORE5)
ECase(EM_78KOR)
ECase(EM_56800EX)
ECase(EM_MBLAZE)
#undef ECase
}

Expand Down
9 changes: 0 additions & 9 deletions lib/Support/Triple.cpp
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Expand Up @@ -38,7 +38,6 @@ const char *Triple::getArchTypeName(ArchType Kind) {
case x86: return "i386";
case x86_64: return "x86_64";
case xcore: return "xcore";
case mblaze: return "mblaze";
case nvptx: return "nvptx";
case nvptx64: return "nvptx64";
case le32: return "le32";
Expand All @@ -63,8 +62,6 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
case ppc64:
case ppc: return "ppc";

case mblaze: return "mblaze";

case mips:
case mipsel:
case mips64:
Expand Down Expand Up @@ -171,7 +168,6 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
.Case("ppc64", ppc64)
.Case("ppc32", ppc)
.Case("ppc", ppc)
.Case("mblaze", mblaze)
.Case("r600", r600)
.Case("hexagon", hexagon)
.Case("sparc", sparc)
Expand Down Expand Up @@ -201,7 +197,6 @@ const char *Triple::getArchNameForAssembler() {
.Case("x86_64", "x86_64")
.Case("powerpc", "ppc")
.Case("powerpc64", "ppc64")
.Cases("mblaze", "microblaze", "mblaze")
.Case("arm", "arm")
.Cases("armv4t", "thumbv4t", "armv4t")
.Cases("armv5", "armv5e", "thumbv5", "thumbv5e", "armv5")
Expand All @@ -225,7 +220,6 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Cases("amd64", "x86_64", Triple::x86_64)
.Case("powerpc", Triple::ppc)
.Cases("powerpc64", "ppu", Triple::ppc64)
.Case("mblaze", Triple::mblaze)
.Case("aarch64", Triple::aarch64)
.Cases("arm", "xscale", Triple::arm)
// FIXME: It would be good to replace these with explicit names for all the
Expand Down Expand Up @@ -678,7 +672,6 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::arm:
case llvm::Triple::hexagon:
case llvm::Triple::le32:
case llvm::Triple::mblaze:
case llvm::Triple::mips:
case llvm::Triple::mipsel:
case llvm::Triple::nvptx:
Expand Down Expand Up @@ -733,7 +726,6 @@ Triple Triple::get32BitArchVariant() const {
case Triple::arm:
case Triple::hexagon:
case Triple::le32:
case Triple::mblaze:
case Triple::mips:
case Triple::mipsel:
case Triple::nvptx:
Expand Down Expand Up @@ -766,7 +758,6 @@ Triple Triple::get64BitArchVariant() const {
case Triple::arm:
case Triple::hexagon:
case Triple::le32:
case Triple::mblaze:
case Triple::msp430:
case Triple::r600:
case Triple::tce:
Expand Down
2 changes: 1 addition & 1 deletion lib/Target/LLVMBuild.txt
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Expand Up @@ -16,7 +16,7 @@
;===------------------------------------------------------------------------===;

[common]
subdirectories = AArch64 ARM CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC R600 Sparc SystemZ X86 XCore
subdirectories = AArch64 ARM CppBackend Hexagon MSP430 NVPTX Mips PowerPC R600 Sparc SystemZ X86 XCore

; This is a special group whose required libraries are extended (by llvm-build)
; with the best execution engine (the native JIT, if available, or the
Expand Down
8 changes: 0 additions & 8 deletions lib/Target/MBlaze/AsmParser/CMakeLists.txt
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This file was deleted.

23 changes: 0 additions & 23 deletions lib/Target/MBlaze/AsmParser/LLVMBuild.txt
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