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Merge tag 'nand/for-5.2' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/mtd/linux into mtd/next NAND core changes: - Support having the bad block markers in either the first, second or last page of a block. The combination of all three location is now possible. - Constification of NAND_OP_PARSER(_PATTERN) elements. - Generic NAND DT bindings changed to yaml format (can be used to check the proposed bindings. First platform to be fully supported: sunxi. - Stopped using several legacy hooks. - Preparation to use the generic NAND layer with the addition of several helpers and the removal of the struct nand_chip from generic functions. - Kconfig cleanup to prepare the introduction of external ECC engines support. - Fallthrough comments. - Introduction of the SPI-mem dirmap API for SPI-NAND devices. Raw NAND controller drivers changes: - nandsim: * Switch to ->exec-op(). - meson: * Misc cleanups and fixes. * New OOB layout. - Sunxi: * A23/A33 NAND DMA support. - Ingenic: * Full reorganization and cleanup. * Clear separation between NAND controller and ECC engine. * Support JZ4740 an JZ4725B. - Denali: * Clear controller/chip separation. * ->exec_op() migration. * Various cleanups. - fsl_elbc: * Enable software ECC support. - Atmel: * Sam9x60 support. - GPMI: * Introduce the GPMI_IS_MXS() macro. - Various trivial/spelling/coding style fixes.
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Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
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| # SPDX-License-Identifier: GPL-2.0 | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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| title: Allwinner A10 NAND Controller Device Tree Bindings | ||
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| allOf: | ||
| - $ref: "nand-controller.yaml" | ||
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| maintainers: | ||
| - Chen-Yu Tsai <[email protected]> | ||
| - Maxime Ripard <[email protected]> | ||
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| properties: | ||
| "#address-cells": true | ||
| "#size-cells": true | ||
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| compatible: | ||
| enum: | ||
| - allwinner,sun4i-a10-nand | ||
| - allwinner,sun8i-a23-nand-controller | ||
| reg: | ||
| maxItems: 1 | ||
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| interrupts: | ||
| maxItems: 1 | ||
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| clocks: | ||
| items: | ||
| - description: Bus Clock | ||
| - description: Module Clock | ||
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| clock-names: | ||
| items: | ||
| - const: ahb | ||
| - const: mod | ||
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| resets: | ||
| maxItems: 1 | ||
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| reset-names: | ||
| const: ahb | ||
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| dmas: | ||
| maxItems: 1 | ||
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| dma-names: | ||
| const: rxtx | ||
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| pinctrl-names: true | ||
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| patternProperties: | ||
| "^pinctrl-[0-9]+$": true | ||
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| "^nand@[a-f0-9]+$": | ||
| properties: | ||
| reg: | ||
| maxItems: 1 | ||
| minimum: 0 | ||
| maximum: 7 | ||
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| nand-ecc-mode: true | ||
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| nand-ecc-algo: | ||
| const: bch | ||
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| nand-ecc-step-size: | ||
| enum: [ 512, 1024 ] | ||
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| nand-ecc-strength: | ||
| maximum: 80 | ||
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| allwinner,rb: | ||
| description: | ||
| Contains the native Ready/Busy IDs. | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32-array | ||
| - minItems: 1 | ||
| maxItems: 2 | ||
| items: | ||
| minimum: 0 | ||
| maximum: 1 | ||
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| additionalProperties: false | ||
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| required: | ||
| - compatible | ||
| - reg | ||
| - interrupts | ||
| - clocks | ||
| - clock-names | ||
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| additionalProperties: false | ||
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| ... |
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143
Documentation/devicetree/bindings/mtd/nand-controller.yaml
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| # SPDX-License-Identifier: GPL-2.0 | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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| title: NAND Chip and NAND Controller Generic Binding | ||
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| maintainers: | ||
| - Miquel Raynal <[email protected]> | ||
| - Richard Weinberger <[email protected]> | ||
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| description: | | ||
| The NAND controller should be represented with its own DT node, and | ||
| all NAND chips attached to this controller should be defined as | ||
| children nodes of the NAND controller. This representation should be | ||
| enforced even for simple controllers supporting only one chip. | ||
| The ECC strength and ECC step size properties define the user | ||
| desires in terms of correction capability of a controller. Together, | ||
| they request the ECC engine to correct {strength} bit errors per | ||
| {size} bytes. | ||
| The interpretation of these parameters is implementation-defined, so | ||
| not all implementations must support all possible | ||
| combinations. However, implementations are encouraged to further | ||
| specify the value(s) they support. | ||
| properties: | ||
| $nodename: | ||
| pattern: "^nand-controller(@.*)?" | ||
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| "#address-cells": | ||
| const: 1 | ||
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| "#size-cells": | ||
| const: 0 | ||
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| ranges: true | ||
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| patternProperties: | ||
| "^nand@[a-f0-9]$": | ||
| properties: | ||
| reg: | ||
| description: | ||
| Contains the native Ready/Busy IDs. | ||
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| nand-ecc-mode: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/string | ||
| - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ] | ||
| description: | ||
| Desired ECC engine, either hardware (most of the time | ||
| embedded in the NAND controller) or software correction | ||
| (Linux will handle the calculations). soft_bch is deprecated | ||
| and should be replaced by soft and nand-ecc-algo. | ||
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| nand-ecc-algo: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/string | ||
| - enum: [ hamming, bch, rs ] | ||
| description: | ||
| Desired ECC algorithm. | ||
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| nand-bus-width: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| - enum: [ 8, 16 ] | ||
| - default: 8 | ||
| description: | ||
| Bus width to the NAND chip | ||
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| nand-on-flash-bbt: | ||
| $ref: /schemas/types.yaml#/definitions/flag | ||
| description: | ||
| With this property, the OS will search the device for a Bad | ||
| Block Table (BBT). If not found, it will create one, reserve | ||
| a few blocks at the end of the device to store it and update | ||
| it as the device ages. Otherwise, the out-of-band area of a | ||
| few pages of all the blocks will be scanned at boot time to | ||
| find Bad Block Markers (BBM). These markers will help to | ||
| build a volatile BBT in RAM. | ||
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| nand-ecc-strength: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| - minimum: 1 | ||
| description: | ||
| Maximum number of bits that can be corrected per ECC step. | ||
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| nand-ecc-step-size: | ||
| allOf: | ||
| - $ref: /schemas/types.yaml#/definitions/uint32 | ||
| - minimum: 1 | ||
| description: | ||
| Number of data bytes covered by a single ECC step. | ||
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| nand-ecc-maximize: | ||
| $ref: /schemas/types.yaml#/definitions/flag | ||
| description: | ||
| Whether or not the ECC strength should be maximized. The | ||
| maximum ECC strength is both controller and chip | ||
| dependent. The ECC engine has to select the ECC config | ||
| providing the best strength and taking the OOB area size | ||
| constraint into account. This is particularly useful when | ||
| only the in-band area is used by the upper layers, and you | ||
| want to make your NAND as reliable as possible. | ||
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| nand-is-boot-medium: | ||
| $ref: /schemas/types.yaml#/definitions/flag | ||
| description: | ||
| Whether or not the NAND chip is a boot medium. Drivers might | ||
| use this information to select ECC algorithms supported by | ||
| the boot ROM or similar restrictions. | ||
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| nand-rb: | ||
| $ref: /schemas/types.yaml#/definitions/uint32-array | ||
| description: | ||
| Contains the native Ready/Busy IDs. | ||
|
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| required: | ||
| - reg | ||
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| required: | ||
| - "#address-cells" | ||
| - "#size-cells" | ||
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| examples: | ||
| - | | ||
| nand-controller { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| /* controller specific properties */ | ||
| nand@0 { | ||
| reg = <0>; | ||
| nand-ecc-mode = "soft"; | ||
| nand-ecc-algo = "bch"; | ||
| /* controller specific properties */ | ||
| }; | ||
| }; |
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