fix detection of write access

RastaKolobar · Mar 30, 2019 · d075aa8 · d075aa8
1 parent 0fc1a94
commit d075aa8
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/modbus_cli/access.py b/modbus_cli/access.py
@@ -43,7 +43,7 @@ def endianness(self):
 
     @property
     def write(self):
-        return bool(self.values_to_write)
+        return any(x is not None for x in self.values_to_write)
 
     def size(self):
         """Number of registers"""