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circuit_training_openlane Public
Instructions on how to run Circuit Training in OpenLane flow
2 UpdatedAug 1, 2024 -
toolchain-iverilog Public
Forked from FPGAwars/toolchain-iverilog🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
Verilog GNU General Public License v3.0 UpdatedOct 5, 2023 -
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DREAMPlaceFPGA Public
Forked from rachelselinar/DREAMPlaceFPGAAn Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
C++ BSD 3-Clause "New" or "Revised" License UpdatedMay 24, 2023 -
circuit_training Public
Forked from google-research/circuit_training -
yosys Public
Forked from YosysHQ/yosysYosys Open SYnthesis Suite
C++ ISC License UpdatedMar 28, 2023 -
OpenLane Public
Forked from The-OpenROAD-Project/OpenLane** README **: OpenLane+DREAMPlace (PL_DREAMPLACE_GLB_PLACEMENT in config.json) option for global placement in fpi branch
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transistor_counter Public
Simple transistor counter in Verilog gate-level netlist using data from CDL
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DQN_GlobalRouting Public
Forked from haiguanl/DQN_GlobalRoutingApplying Deep Q-learning for Global Routing
Python UpdatedFeb 16, 2023 -
netlist Public
Forked from eda-rs/netlistgeneric NetList data structure for VLSI
Verilog Apache License 2.0 UpdatedJan 26, 2023 -
MacroPlacement Public
Forked from TILOS-AI-Institute/MacroPlacement*** README ***: for convertors checkout this branch: pb2def
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Surelog Public
Forked from chipsalliance/SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++ Apache License 2.0 UpdatedDec 8, 2022 -
UHDM Public
Forked from chipsalliance/UHDMUniversal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …
C++ Apache License 2.0 UpdatedDec 7, 2022 -
DREAMPlace Public
Forked from limbo018/DREAMPlaceDeep learning toolkit-enabled VLSI placement
C++ BSD 3-Clause "New" or "Revised" License UpdatedOct 21, 2022 -
wotan Public
Forked from wotan-fpga/wotanA tool for early-stage FPGA routing architecture evaluation using analytic and heuristic methods (and no benchmarks).
C++ MIT License UpdatedSep 22, 2021 -
vtr-verilog-to-routing Public
Forked from verilog-to-routing/vtr-verilog-to-routingVerilog to Routing -- Open Source CAD Flow for FPGA Research
C++ Other UpdatedFeb 11, 2021