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ssb: when needed, reject IM input while disabling device
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Signed-off-by: Rafał Miłecki <[email protected]>
Signed-off-by: John W. Linville <[email protected]>
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rmilecki authored and linvjw committed Feb 18, 2011
1 parent 0d4171e commit b1a1bcf
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Showing 2 changed files with 17 additions and 1 deletion.
16 changes: 15 additions & 1 deletion drivers/ssb/main.c
Original file line number Diff line number Diff line change
Expand Up @@ -1220,7 +1220,7 @@ static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,

void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
{
u32 reject;
u32 reject, val;

if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
return;
Expand All @@ -1229,12 +1229,26 @@ void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);

if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
val = ssb_read32(dev, SSB_IMSTATE);
val |= SSB_IMSTATE_REJECT;
ssb_write32(dev, SSB_IMSTATE, val);
ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 0);
}

ssb_write32(dev, SSB_TMSLOW,
SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
reject | SSB_TMSLOW_RESET |
core_specific_flags);
ssb_flush_tmslow(dev);

if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
val = ssb_read32(dev, SSB_IMSTATE);
val &= ~SSB_IMSTATE_REJECT;
ssb_write32(dev, SSB_IMSTATE, val);
}

ssb_write32(dev, SSB_TMSLOW,
reject | SSB_TMSLOW_RESET |
core_specific_flags);
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2 changes: 2 additions & 0 deletions include/linux/ssb/ssb_regs.h
Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,8 @@
#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
#define SSB_IMSTATE_TO 0x00040000 /* Timeout */
#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
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