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os/board/rtl8730e: add driver layer implemenation for i2s tdm #6541

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os/board/rtl8730e: add driver layer implemenation for i2s tdm #6541

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058db6b
os/board/rtl8730e: add driver layer implemenation for i2s tdm
lhenry-realtek Nov 27, 2024
110a416
os/board/rtl8730e: fix clock configuration for signal generation
lhenry-realtek Nov 27, 2024
8df3379
os/board/rtl8730e: add missing i2s init flow api calls
lhenry-realtek Nov 29, 2024
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os/board/rtl8730e: fix clock configuration for signal generation 
Fix clock selection parameters to get targeted signal value:
MCLK = 12.288MHz (OK)
BCLK = 2.048MHz (OK)
WCLK (need to setup Rx api in order to trigger WCLK activity)
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@lhenry-realtek
lhenry-realtek committed Nov 27, 2024
commit 110a416e567ae927e2f26767eac8541e0780ef97
7 changes: 6 additions & 1 deletion os/board/rtl8730e/src/component/mbed/targets/hal/rtl8730e/i2s_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -394,8 +394,13 @@ static uint32_t i2s_clock_select(i2s_t *obj)

Init_Params.sr = obj->sampling_rate;
dbg("ChLen: %d ChCnt: %d Sr: %d\n", obj->channel_length, obj->channel_num, obj->sampling_rate);
#if defined(CONFIG_AMEBASMART_I2S_TDM)
Init_Params.codec_multiplier_with_rate = 0;
Init_Params.sport_mclk_fixed_max = (uint32_t) 12288000; //12.288MHz
#else
Init_Params.codec_multiplier_with_rate = 256;
Init_Params.sport_mclk_fixed_max = (uint32_t) NULL;
#endif
Audio_Clock_Choose(PLL_CLK, &Init_Params, &Clock_Params);
obj->clock = Clock_Params.Clock;

Expand All @@ -422,7 +427,7 @@ static uint32_t i2s_clock_select(i2s_t *obj)
clock_mode = PLL_CLOCK_98P304M / Clock_Params.PLL_DIV;
break;
}
dbg("CLK: %d mode: %f div: %d\n", Clock_Params.Clock, clock_mode, Clock_Params.PLL_DIV);
dbg("CLK: %d div: %d\n", Clock_Params.Clock, Clock_Params.PLL_DIV);
return clock_mode;
}

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