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5 stars written in Verilog
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IBM / AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Verilog 412 102 Updated Dec 2, 2019

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Verilog 197 26 Updated Oct 21, 2024

pku-liang / TensorLib

Forked from kirliavc/tensorlib

A Spatial Accelerator Generation Framework for Tensor Algebra.

Verilog 55 9 Updated Dec 3, 2021

tayler-hetherington / dnn-sim

Verilog 17 7 Updated Jun 10, 2016

BradMcDanel / multiplication-free-dnn

Verilog 10 2 Updated Jun 28, 2019