Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.

This is the implementation of the paper [Optimus: Towards Optimal Layer-Fusion on Deep Learning Processors].

for Data Science class on Coursera

Module to Automatically maximize the utilization of GPU resources in a Kubernetes cluster through real-time dynamic partitioning and elastic quotas - Effortless optimization at its finest!

《Machine Learning Systems: Design and Implementation》- Chinese Version

System for AI Education Resource.

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Benchmarks for popular CNN models

The lcc retargetable ANSI C compiler

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

A template project for beginning new Chisel work

A Spatial Accelerator Generation Framework for Tensor Algebra.

IC implementation of Systolic Array for TPU

Accelerate Linear Equation System Solver on DE1-SoC development Board

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

Transformer related optimization, including BERT, GPT

Count the MACs / FLOPs of your PyTorch model.

Model summary in PyTorch similar to `model.summary()` in Keras

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Intermediate Language (IL) for Hardware Accelerator Generators

Tengine is a lite, high performance, modular inference engine for embedded device

XLS: Accelerated HW Synthesis

A home for Genesis2 sources.

Distributed Communication-Optimal Matrix-Matrix Multiplication Algorithm

A flexible and efficient deep neural network (DNN) compiler that generates high-performance executable from a DNN model description.