Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.

A logic synthesis tool

AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

Bus bridges and other odds and ends

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

This is the AXI-to-APB bridge which only supports convert AXI-32bit to APB-32 bit

Started a new repo for AXI to APB bridge

amba3 apb/axi vip

RTL, Cmodel, and testbench for NVDLA

Example design for the Ethernet FMC using the hard GEMs of the Zynq

The Ultra-Low Power RISC-V Core

Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder

Xilinx AXI VIP example of use

Generates a Verilog implementation of a Wallace tree of 3-2 carry save adders.

AXI4 and AXI4-Lite interface definitions

This verilog code takes a 5x5 matrix as an input and generates it's inverse

Inverse of a matrix in verilog

Verilog AXI components for FPGA implementation

Hyper-Parameter Tuning / BayesianOptimization / Gaussian Process / etc.

optimize parameters

GA_python for multi-parameters optimization

Used a Deep Neural Network implemented on Keras framework to train the variables relating to arrangement of MOSFETS on an Integrated Circuit. Applied Particle Swarm Optimisation and Genetic Algorit…

A circuit optimizer using genetic algorithm.

A framework for single/multi-objective optimization with metaheuristics

Simplicial Homology Global Optimization

Hyperparameter Optimization

A step-by-step guide for surrogate optimization using Gaussian Process surrogate model