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  • chisel Public

    Forked from chipsalliance/chisel

    Chisel: A Modern Hardware Design Language

    Scala Apache License 2.0 Updated Dec 4, 2024

  • pressure-off-the-brain Public

    Forked from trevortylerlee/astro-micro

    Blog theme for Astro with search and comments built-in. Zero frameworks.

    JavaScript MIT License Updated Jul 4, 2024

  • cocotb Public

    Forked from cocotb/cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    Python BSD 3-Clause "New" or "Revised" License Updated May 26, 2024

  • turnstile Public

    A small repository consisting of a Nextjs web client, a Nest.js node.js app, and uses a database for a simple personal access token management system

    TypeScript Updated Aug 20, 2023

  • smattacus-fork-awesome-open-hardware-verification Public

    Forked from ben-marshall/awesome-open-hardware-verification

    A List of Free and Open Source Hardware Verification Tools and Frameworks

    MIT License Updated Aug 14, 2023

  • cautious-rotary-phone Public

    docker compose github action testing for an MVC with a client communicating via RESTful calls with an app

    Python 1 Updated Feb 12, 2023

  • goldfinch Public

    Image sharpening algorithm behavioral model in Python as well as a SystemC representation

    C++ Updated Nov 28, 2022

  • systemc-blocks Public

    Small repo for playing around with systemc blocks

    C++ Updated Nov 26, 2022

  • systemc-tutorials Public

    A repository containing short tutorials of SystemC. Uses a SystemC container + CMake.

    C++ Updated Aug 24, 2022

  • pytest-plugins Public

    Forked from man-group/pytest-plugins

    A grab-bag of nifty pytest plugins

    Python MIT License Updated Aug 16, 2022

  • carp Public

    ARP Block with testbench

    SystemVerilog Updated Sep 6, 2021

  • pelican Public

    CI/CD Test Repo for HDL Applications

    Python Updated May 22, 2021

  • core-v-verif Public

    Forked from openhwgroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly Other Updated Apr 17, 2021

  • cv32e40p Public

    Forked from openhwgroup/cv32e40p

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog Other Updated Apr 25, 2020

  • pipelined-mips Public

    Pipelined MIPS processor based on Harris & Harris Digital Design and Computer Architecture, 2nd Ed.

    SystemVerilog 2 Updated Mar 16, 2020

  • Tutorials Public

    HTML pages with tutorials for creating acquisition data.

    Updated Oct 12, 2017

  • data-analysis Public

    A repository holding code which has been used for analysis of Skiff lab data.

    MATLAB GNU General Public License v2.0 Updated Jun 29, 2017