A Python toolbox for building complex digital hardware

Build your hardware, easily!

RISCV CPU implementation in SystemVerilog

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

WaveDrom as Sequencer

Repo that shows how to use the VexRiscv with OpenOCD and semihosting.

Simple 3-stage pipeline RISC-V processor

Multi-platform nightly builds of open source digital design and verification tools

SystemVerilog Logger

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Collection of userstyles affecting the browser