final patch for very long conditional branches for mips16 constant is…

…lands.

this completes the basic port of ARM constant islands to Mips16.
More testing, code review, cleanup is in order but basically everything
seems to be working. A bug in gas is preventing some of the runtime
testing but I hope to resolve this soon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196331 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsConstantIslandPass.cpp

@@ -712,41 +712,49 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
           isCond = false;
           break;
         case Mips::BeqzRxImm16:
+          UOpc=Mips::Bimm16;
           Bits = 8;
           Scale = 2;
           isCond = true;
           break;
         case Mips::BeqzRxImmX16:
+          UOpc=Mips::Bimm16;
           Bits = 16;
           Scale = 2;
           isCond = true;
           break;
         case Mips::BnezRxImm16:
+          UOpc=Mips::Bimm16;
           Bits = 8;
           Scale = 2;
           isCond = true;
           break;
         case Mips::BnezRxImmX16:
+          UOpc=Mips::Bimm16;
           Bits = 16;
           Scale = 2;
           isCond = true;
           break;
         case Mips::Bteqz16:
+          UOpc=Mips::Bimm16;
           Bits = 8;
           Scale = 2;
           isCond = true;
           break;
         case Mips::BteqzX16:
+          UOpc=Mips::Bimm16;
           Bits = 16;
           Scale = 2;
           isCond = true;
           break;
         case Mips::Btnez16:
+          UOpc=Mips::Bimm16;
           Bits = 8;
           Scale = 2;
           isCond = true;
           break;
         case Mips::BtnezX16:
+          UOpc=Mips::Bimm16;
           Bits = 16;
           Scale = 2;
           isCond = true;
@@ -1617,7 +1625,7 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
   MachineBasicBlock *MBB = MI->getParent();
   MachineInstr *BMI = &MBB->back();
   bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
-
+  unsigned OppositeBranchOpcode=TII->getOppositeBranchOpc(Opcode);
 
   ++NumCBrFixed;
   if (BMI != MI) {
@@ -1636,15 +1644,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
       if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
         DEBUG(dbgs() << "  Invert Bcc condition and swap its destination with "
                      << *BMI);
-        MI->setDesc(TII->get(TII->getOppositeBranchOpc(Opcode)));
+        MI->setDesc(TII->get(OppositeBranchOpcode));
         BMI->getOperand(BMITargetOperand).setMBB(DestBB);
         MI->getOperand(TargetOperand).setMBB(NewDest);
         return true;
       }
     }
   }
 
-  llvm_unreachable("unsupported range of unconditional branch");
 
   if (NeedSplit) {
     splitBlockBeforeInstr(MI);
@@ -1663,8 +1670,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
 
   // Insert a new conditional branch and a new unconditional branch.
   // Also update the ImmBranch as well as adding a new entry for the new branch.
-  BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
-    .addMBB(NextBB);
+  if (MI->getNumExplicitOperands() == 2) {
+    BuildMI(MBB, DebugLoc(), TII->get(OppositeBranchOpcode))
+           .addReg(MI->getOperand(0).getReg())
+           .addMBB(NextBB);
+  }
+  else { BuildMI(MBB, DebugLoc(), TII->get(OppositeBranchOpcode))
+        .addMBB(NextBB);
+  }
   Br.MI = &MBB->back();
   BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
   BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);

test/CodeGen/Mips/lcb4a.ll

@@ -0,0 +1,69 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static     < %s | FileCheck %s -check-prefix=ci
+
+@i = global i32 0, align 4
+@j = common global i32 0, align 4
+@k = common global i32 0, align 4
+
+; Function Attrs: nounwind optsize
+define i32 @foo() #0 {
+entry:
+  %0 = load i32* @i, align 4, !tbaa !1
+  %cmp = icmp eq i32 %0, 0
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void asm sideeffect ".space 1000", ""() #1, !srcloc !5
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void asm sideeffect ".space 1004", ""() #1, !srcloc !6
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %storemerge = phi i32 [ 1, %if.else ], [ 0, %if.then ]
+  store i32 %storemerge, i32* @i, align 4, !tbaa !1
+  ret i32 0
+}
+
+; ci:	beqz	$3, $BB0_2
+; ci: # BB#1:                                 # %if.else
+
+
+; Function Attrs: nounwind optsize
+define i32 @goo() #0 {
+entry:
+  %0 = load i32* @i, align 4, !tbaa !1
+  %cmp = icmp eq i32 %0, 0
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void asm sideeffect ".space 1000000", ""() #1, !srcloc !7
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void asm sideeffect ".space 1000004", ""() #1, !srcloc !8
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %storemerge = phi i32 [ 1, %if.else ], [ 0, %if.then ]
+  store i32 %storemerge, i32* @i, align 4, !tbaa !1
+  ret i32 0
+}
+
+; ci:	bnez	$3, $BB1_1  # 16 bit inst
+; ci:	jal	$BB1_2	# branch
+; ci:	nop
+; ci: $BB1_1:                                 # %if.else
+
+attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+
+
+!1 = metadata !{metadata !2, metadata !2, i64 0}
+!2 = metadata !{metadata !"int", metadata !3, i64 0}
+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}
+!5 = metadata !{i32 58}
+!6 = metadata !{i32 108}
+!7 = metadata !{i32 190}
+!8 = metadata !{i32 243}