power off.

When power off is requested, POWER_ON is cleared and the on duty is set
to 0 cycles. This does not completely stop power, however, as the pwm_on
interrupt will still occur and pwm_off will be scheduled to be called
immediately after. This sets up a case where pwm_on will switch on the
FET and then the AVR will execute one non-interrupt instruction before
executing the next interrupt (which could be either pwm_off or int0 and
pwm_off).

If this instruction happens to be the "cli" of a commutation block that
would advance to the next PWM FET, the FET on state would be copied to
the new one, but the FET flags would be left cleared, leaving the PWM
interrupt with nothing to do, resulting in the equivalent of full power
until either the high side FET is turned off at the next commutation or
(worse) power is requested again and the correct FET flag is set two
commutations later.

Instead of only setting a 0 duty cycle, always track the FET that should
be PWMed, and make set_new_duty_zero set pwm_on_ptr to pwm_off so that
power is immediately cut, but can still be restored without waiting until
the next cycle.