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AMDGPU/R600: Convert buffer id to VTX_READ input
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Use patterns instead of multiple instructions
Add buffer id to asm string

https://reviews.llvm.org/D22650

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278749 91177308-0d34-0410-b5e6-96231b3b80d8
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jvesely committed Aug 15, 2016
1 parent 072a33f commit fc94e66
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Showing 5 changed files with 146 additions and 198 deletions.
136 changes: 50 additions & 86 deletions lib/Target/AMDGPU/CaymanInstructions.td
Original file line number Diff line number Diff line change
Expand Up @@ -85,14 +85,13 @@ def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> {
let eop = 0; // This bit is not used on Cayman.
}

class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
: VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
class VTX_READ_cm <string name, dag outs>
: VTX_WORD0_cm, VTX_READ<name, outs, []> {

// Static fields
let VC_INST = 0;
let FETCH_TYPE = 2;
let FETCH_WHOLE_QUAD = 0;
let BUFFER_ID = buffer_id;
let SRC_REL = 0;
// XXX: We can infer this field based on the SRC_GPR. This would allow us
// to store vertex addresses in any channel, not just X.
Expand All @@ -105,9 +104,9 @@ class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
let Inst{31-0} = Word0;
}

class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
(outs R600_TReg32_X:$dst_gpr), pattern> {
def VTX_READ_8_cm
: VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr",
(outs R600_TReg32_X:$dst_gpr)> {

let DST_SEL_X = 0;
let DST_SEL_Y = 7; // Masked
Expand All @@ -116,9 +115,9 @@ class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
let DATA_FORMAT = 1; // FMT_8
}

class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
(outs R600_TReg32_X:$dst_gpr), pattern> {
def VTX_READ_16_cm
: VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr",
(outs R600_TReg32_X:$dst_gpr)> {
let DST_SEL_X = 0;
let DST_SEL_Y = 7; // Masked
let DST_SEL_Z = 7; // Masked
Expand All @@ -127,9 +126,9 @@ class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>

}

class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
(outs R600_TReg32_X:$dst_gpr), pattern> {
def VTX_READ_32_cm
: VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr",
(outs R600_TReg32_X:$dst_gpr)> {

let DST_SEL_X = 0;
let DST_SEL_Y = 7; // Masked
Expand All @@ -147,9 +146,9 @@ class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
let Constraints = "$src_gpr.ptr = $dst_gpr";
}

class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
(outs R600_Reg64:$dst_gpr), pattern> {
def VTX_READ_64_cm
: VTX_READ_cm <"VTX_READ_64 $dst_gpr.XY, $src_gpr",
(outs R600_Reg64:$dst_gpr)> {

let DST_SEL_X = 0;
let DST_SEL_Y = 1;
Expand All @@ -158,9 +157,9 @@ class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
let DATA_FORMAT = 0x1D; // COLOR_32_32
}

class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
(outs R600_Reg128:$dst_gpr), pattern> {
def VTX_READ_128_cm
: VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",
(outs R600_Reg128:$dst_gpr)> {

let DST_SEL_X = 0;
let DST_SEL_Y = 1;
Expand All @@ -177,79 +176,44 @@ class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
//===----------------------------------------------------------------------===//
// VTX Read from parameter memory space
//===----------------------------------------------------------------------===//
def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
[(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
[(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
[(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
[(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
>;
def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
(VTX_READ_8_cm MEMxi:$src_gpr, 3)>;
def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
(VTX_READ_16_cm MEMxi:$src_gpr, 3)>;
def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_32_cm MEMxi:$src_gpr, 3)>;
def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_64_cm MEMxi:$src_gpr, 3)>;
def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_128_cm MEMxi:$src_gpr, 3)>;

def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
[(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
>;
//===----------------------------------------------------------------------===//
// VTX Read from constant memory space
//===----------------------------------------------------------------------===//
def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),
(VTX_READ_8_cm MEMxi:$src_gpr, 2)>;
def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),
(VTX_READ_16_cm MEMxi:$src_gpr, 2)>;
def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_32_cm MEMxi:$src_gpr, 2)>;
def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_64_cm MEMxi:$src_gpr, 2)>;
def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_128_cm MEMxi:$src_gpr, 2)>;

//===----------------------------------------------------------------------===//
// VTX Read from global memory space
//===----------------------------------------------------------------------===//

// 8-bit reads
def VTX_READ_ID1_8_cm : VTX_READ_8_cm <1,
[(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))]
>;

// 16-bit reads
def VTX_READ_ID1_16_cm : VTX_READ_16_cm <1,
[(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))]
>;

// 32-bit reads
def VTX_READ_ID1_32_cm : VTX_READ_32_cm <1,
[(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
>;

// 64-bit reads
def VTX_READ_ID1_64_cm : VTX_READ_64_cm <1,
[(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
>;

// 128-bit reads
def VTX_READ_ID1_128_cm : VTX_READ_128_cm <1,
[(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
>;

// 8-bit reads
def VTX_READ_ID2_8_cm : VTX_READ_8_cm <2,
[(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))]
>;

// 16-bit reads
def VTX_READ_ID2_16_cm : VTX_READ_16_cm <2,
[(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))]
>;

// 32-bit reads
def VTX_READ_ID2_32_cm : VTX_READ_32_cm <2,
[(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
>;

// 64-bit reads
def VTX_READ_ID2_64_cm : VTX_READ_64_cm <2,
[(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
>;

// 128-bit reads
def VTX_READ_ID2_128_cm : VTX_READ_128_cm <2,
[(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
>;
def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),
(VTX_READ_8_cm MEMxi:$src_gpr, 1)>;
def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),
(VTX_READ_16_cm MEMxi:$src_gpr, 1)>;
def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_32_cm MEMxi:$src_gpr, 1)>;
def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_64_cm MEMxi:$src_gpr, 1)>;
def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_128_cm MEMxi:$src_gpr, 1)>;

} // End isCayman

137 changes: 50 additions & 87 deletions lib/Target/AMDGPU/EvergreenInstructions.td
Original file line number Diff line number Diff line change
Expand Up @@ -116,14 +116,13 @@ def RAT_STORE_TYPED_eg: CF_MEM_RAT_STORE_TYPED<1>;

} // End usesCustomInserter = 1

class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
: VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
class VTX_READ_eg <string name, dag outs>
: VTX_WORD0_eg, VTX_READ<name, outs, []> {

// Static fields
let VC_INST = 0;
let FETCH_TYPE = 2;
let FETCH_WHOLE_QUAD = 0;
let BUFFER_ID = buffer_id;
let SRC_REL = 0;
// XXX: We can infer this field based on the SRC_GPR. This would allow us
// to store vertex addresses in any channel, not just X.
Expand All @@ -132,9 +131,9 @@ class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
let Inst{31-0} = Word0;
}

class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
(outs R600_TReg32_X:$dst_gpr), pattern> {
def VTX_READ_8_eg
: VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr",
(outs R600_TReg32_X:$dst_gpr)> {

let MEGA_FETCH_COUNT = 1;
let DST_SEL_X = 0;
Expand All @@ -144,9 +143,9 @@ class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
let DATA_FORMAT = 1; // FMT_8
}

class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
(outs R600_TReg32_X:$dst_gpr), pattern> {
def VTX_READ_16_eg
: VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr",
(outs R600_TReg32_X:$dst_gpr)> {
let MEGA_FETCH_COUNT = 2;
let DST_SEL_X = 0;
let DST_SEL_Y = 7; // Masked
Expand All @@ -156,9 +155,9 @@ class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>

}

class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
(outs R600_TReg32_X:$dst_gpr), pattern> {
def VTX_READ_32_eg
: VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr",
(outs R600_TReg32_X:$dst_gpr)> {

let MEGA_FETCH_COUNT = 4;
let DST_SEL_X = 0;
Expand All @@ -177,9 +176,9 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
let Constraints = "$src_gpr.ptr = $dst_gpr";
}

class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id,
(outs R600_Reg64:$dst_gpr), pattern> {
def VTX_READ_64_eg
: VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr",
(outs R600_Reg64:$dst_gpr)> {

let MEGA_FETCH_COUNT = 8;
let DST_SEL_X = 0;
Expand All @@ -189,9 +188,9 @@ class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern>
let DATA_FORMAT = 0x1D; // COLOR_32_32
}

class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
(outs R600_Reg128:$dst_gpr), pattern> {
def VTX_READ_128_eg
: VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr",
(outs R600_Reg128:$dst_gpr)> {

let MEGA_FETCH_COUNT = 16;
let DST_SEL_X = 0;
Expand All @@ -209,80 +208,44 @@ class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
//===----------------------------------------------------------------------===//
// VTX Read from parameter memory space
//===----------------------------------------------------------------------===//
def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
(VTX_READ_8_eg MEMxi:$src_gpr, 3)>;
def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
(VTX_READ_16_eg MEMxi:$src_gpr, 3)>;
def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_32_eg MEMxi:$src_gpr, 3)>;
def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_64_eg MEMxi:$src_gpr, 3)>;
def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_128_eg MEMxi:$src_gpr, 3)>;

def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <3,
[(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <3,
[(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <3,
[(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <3,
[(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
>;

def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <3,
[(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
>;
//===----------------------------------------------------------------------===//
// VTX Read from constant memory space
//===----------------------------------------------------------------------===//
def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)),
(VTX_READ_8_eg MEMxi:$src_gpr, 2)>;
def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)),
(VTX_READ_16_eg MEMxi:$src_gpr, 2)>;
def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_32_eg MEMxi:$src_gpr, 2)>;
def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_64_eg MEMxi:$src_gpr, 2)>;
def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_128_eg MEMxi:$src_gpr, 2)>;

//===----------------------------------------------------------------------===//
// VTX Read from global memory space
//===----------------------------------------------------------------------===//

// 8-bit reads
def VTX_READ_ID1_8_eg : VTX_READ_8_eg <1,
[(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))]
>;

// 16-bit reads
def VTX_READ_ID1_16_eg : VTX_READ_16_eg <1,
[(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))]
>;

// 32-bit reads
def VTX_READ_ID1_32_eg : VTX_READ_32_eg <1,
[(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
>;

// 64-bit reads
def VTX_READ_ID1_64_eg : VTX_READ_64_eg <1,
[(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
>;

// 128-bit reads
def VTX_READ_ID1_128_eg : VTX_READ_128_eg <1,
[(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
>;

// 8-bit reads
def VTX_READ_ID2_8_eg : VTX_READ_8_eg <2,
[(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))]
>;

// 16-bit reads
def VTX_READ_ID2_16_eg : VTX_READ_16_eg <2,
[(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))]
>;

// 32-bit reads
def VTX_READ_ID2_32_eg : VTX_READ_32_eg <2,
[(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
>;

// 64-bit reads
def VTX_READ_ID2_64_eg : VTX_READ_64_eg <2,
[(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
>;

// 128-bit reads
def VTX_READ_ID2_128_eg : VTX_READ_128_eg <2,
[(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
>;
def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)),
(VTX_READ_8_eg MEMxi:$src_gpr, 1)>;
def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)),
(VTX_READ_16_eg MEMxi:$src_gpr, 1)>;
def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_32_eg MEMxi:$src_gpr, 1)>;
def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_64_eg MEMxi:$src_gpr, 1)>;
def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
(VTX_READ_128_eg MEMxi:$src_gpr, 1)>;

} // End Predicates = [isEG]

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