drivers: pinctrl: silabs: Add pinctrl driver for digital bus

Silicon Labs Series 2 and newer devices do alternate function configuration fundamentally differently from Series 0 and 1. Pin routing is done in a centralized fashion in the GPIO peripheral, as opposed to having ROUTE registers in every peripheral. The concept of alternate function location numbers also does not exist, functions are directly assigned to GPIOs by their port and pin number. This commit adds a new pinctrl driver for devices that use DBUS. It fully makes use of pinctrl design principles as outlined in the Zephyr documentation. The previous driver hard-codes pin properties such as filter and pull-up/down in the driver itself, while the new driver leaves this up to the user as configurable DeviceTree properties. The previous driver has hard-coded support for UART, SPI and I2C, while the new driver has generic support for all DBUS signals. Signed-off-by: Aksel Skauge Mellbye <[email protected]>
Thalley · Nov 28, 2024 · f3246cd · f3246cd
1 parent f5409bd
commit f3246cd
Show file tree

Hide file tree

Showing 11 changed files with 7,835 additions and 1 deletion.
diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt
@@ -29,6 +29,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQMP pinctrl_xlnx_zynqmp.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_SILABS_DBUS pinctrl_silabs_dbus.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
@@ -57,6 +57,7 @@ source "drivers/pinctrl/Kconfig.xlnx"
 source "drivers/pinctrl/Kconfig.xmc4xxx"
 source "drivers/pinctrl/Kconfig.nxp_s32"
 source "drivers/pinctrl/Kconfig.gecko"
+source "drivers/pinctrl/Kconfig.silabs_dbus"
 source "drivers/pinctrl/Kconfig.ti_k3"
 source "drivers/pinctrl/Kconfig.emsdp"
 source "drivers/pinctrl/Kconfig.ti_cc32xx"

diff --git a/drivers/pinctrl/Kconfig.silabs_dbus b/drivers/pinctrl/Kconfig.silabs_dbus
@@ -0,0 +1,10 @@
+# Copyright (c) 2022 Silicon Labs
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_SILABS_DBUS
+	bool "Silabs DBUS pin controller driver"
+	default y
+	depends on DT_HAS_SILABS_DBUS_PINCTRL_ENABLED
+	help
+	  Silabs DBUS pin controller driver. This driver is used by series
+	  using the DBUS (Digital Bus) for pin multiplexing.
diff --git a/drivers/pinctrl/pinctrl_silabs_dbus.c b/drivers/pinctrl/pinctrl_silabs_dbus.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/arch/cpu.h>
+
+#include <em_gpio.h>
+
+#define DT_DRV_COMPAT silabs_dbus_pinctrl
+#define PIN_MASK      0xF0000UL
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		mem_addr_t enable_reg, route_reg;
+
+		/* Configure GPIO */
+		GPIO_PinModeSet(pins[i].port, pins[i].pin, pins[i].mode, pins[i].dout);
+
+		/* Configure DBUS */
+		enable_reg = DT_INST_REG_ADDR(0) + (pins[i].base_offset * sizeof(mem_addr_t));
+		route_reg = enable_reg + (pins[i].route_offset * sizeof(mem_addr_t));
+
+		sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg);
+
+		if (pins[i].en_bit != 0xFFU) {
+			sys_set_bit(enable_reg, pins[i].en_bit);
+		}
+	}
+
+	return 0;
+}
diff --git a/dts/bindings/pinctrl/silabs,dbus-pinctrl.yaml b/dts/bindings/pinctrl/silabs,dbus-pinctrl.yaml
@@ -0,0 +1,128 @@
+# Copyright (c) 2024 Silicon Labs
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The Silabs pin controller is a singleton node responsible for controlling
+    pin function selection and pin properties. For example, you can use this
+    node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
+    pin. This pin controller is used for devices that use DBUS (Digital Bus)
+    for alternate function configuration, including Series 2 devices.
+
+    The pinctrl settings are referenced in a device tree peripheral node. For
+    example when configuring a USART:
+
+      &usart0 {
+        compatible = "silabs,gecko-usart";
+        pinctrl-0 = <&usart0_default>;
+        pinctrl-names = "default";
+      }
+
+    pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
+    this example &usart0_default. This phandle is defined as a child node of the
+    'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
+    directory or a device tree overlay in the application:
+
+      &pinctrl {
+        /* Configuration for USART0 peripheral, default state */
+        usart0_default: usart0_default {
+          /* Group of output pins with shared properties (name is arbitrary) */
+          group0 {
+            /* Configure PA8 as USART0 TX in GPIO DBUS */
+            pins = <USART0_TX_PA8>;
+            /* Configure GPIO to push-pull mode */
+            drive-push-pull;
+            /* Set DOUT high */
+            output-high;
+          };
+          /* Group of input pins with shared properties (name is arbitrary) */
+          group1 {
+            /* Configure PA9 as USART0 RX in GPIO DBUS */
+            pins = <USART0_RX_PA9>;
+            /* Configure GPIO to input mode */
+            input-enable;
+            /* Enable input glitch filter */
+            silabs,input-filter;
+          };
+        };
+      };
+
+    The 'usart0_default' child node encodes the pin configurations for a
+    particular state of the device, the default (active) state.
+
+    Pin configurations are organized in groups within each child node. Each
+    group can specify a list of pin function selections in the `pins` property,
+    that all will be configured with the same GPIO mode as given by the rest
+    of the properties on the group.
+
+    The possible pin properties are as follows:
+
+    - input-disable: Configure GPIO to disabled mode. Setting this property is
+                     optional, as pins are disabled by default. If the "Input
+                     disabled with pull-up" mode is desired, the property must
+                     be set in combination with bias-pull-up.
+    - input-enable: Configure GPIO to input mode.
+    - drive-push-pull: Configure GPIO to push-pull mode.
+    - drive-open-drain: Configure GPIO to open-drain (wired-AND) mode.
+    - drive-open-source: Configure GPIO to open-source (wired-OR) mode.
+
+    Only one of the above properties must be set at a time, as they are mutually
+    exclusive. Additional properties may be combined with the above ones:
+
+    - bias-pull-down: Enable pull-down resistor. Allowed in input-enable and
+                      drive-open-source modes.
+    - bias-pull-up: Enable pull-up resistor. Allowed in input-disable,
+                    input-enable and drive-open-drain modes.
+    - output-high: Drive GPIO high. Allowed in drive-push-pull mode.
+    - output-low: Drive GPIO low. Allowed in drive-push-pull mode. Setting
+                  this property is optional, leaving it out has the same effect.
+    - silabs,input-filter: Enable input glitch filter. Allowed in input-enable
+                           and drive-open-drain modes.
+    - silabs,alternate-port-control: Use alternate port control settings.
+                                     Allowed in drive-push-pull and
+                                     drive-open-drain modes.
+
+compatible: "silabs,dbus-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Silabs DBUS pin controller pin configuration. Each child node defines
+    the configuration for a particular group of pins.
+  child-binding:
+    description: |
+      Silabs DBUS pin controller pin configuration group.
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - bias-pull-down
+          - bias-pull-up
+          - drive-open-drain
+          - drive-open-source
+          - drive-push-pull
+          - input-disable
+          - input-enable
+          - output-high
+          - output-low
+
+    properties:
+      pins:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should be
+          defined using the <peripheral>_<signal>_<pin> macros available from
+          the SoC DeviceTree files.
+
+      silabs,input-filter:
+        description: |
+          Enable input glitch filter on this pin. May be used in input-enable
+          and drive-open-drain modes.
+        type: boolean
+
+      silabs,alternate-port-control:
+        description: |
+          Use Alternate Port Control settings for Slew Rate and Input Disable
+          for this pin. May be used in drive-push-pull and drive-open-drain
+          modes.
+        type: boolean
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h b/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 Silicon Labs
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+/*
+ * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows:
+ *
+ * 31..29: Reserved
+ * 28..24: Route register offset in words from peripheral config (offset of <fun>ROUTE
+ *         register in GPIO_<periph>ROUTE_TypeDef)
+ * 23..19: Enable bit (offset into ROUTEEN register for given function)
+ * 18    : Enable bit presence (some inputs are auto-enabled)
+ * 17..8 : Peripheral config offset in words from DBUS base within GPIO (offset of <periph>ROUTE[n]
+ *         register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440])
+ *  7..4 : GPIO pin
+ *  3..0 : GPIO port
+ */
+
+#define SILABS_PINCTRL_GPIO_PORT_MASK   0x0000000FUL
+#define SILABS_PINCTRL_GPIO_PIN_MASK    0x000000F0UL
+#define SILABS_PINCTRL_PERIPH_BASE_MASK 0x0003FF00UL
+#define SILABS_PINCTRL_HAVE_EN_MASK     0x00040000UL
+#define SILABS_PINCTRL_EN_BIT_MASK      0x00F80000UL
+#define SILABS_PINCTRL_ROUTE_MASK       0x1F000000UL
+
+#define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route)                             \
+	(FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) |                                         \
+	 FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) |                                           \
+	 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) |                                \
+	 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) |                                     \
+	 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) |                                          \
+	 FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ */