Skip to content
View TimRudy's full-sized avatar

Block or report TimRudy

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. ice-chips-verilog Public

    IceChips is a library of all common discrete logic devices in Verilog

    Verilog 140 24

  2. uart-verilog Public

    A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

    Verilog 28 4

  3. icestudio Public

    Forked from FPGAwars/icestudio

    ❄️ Visual editor for open FPGA boards

    JavaScript 2

115 contributions in the last year

Contribution Graph
Day of Week March April May June July August September October November December January February March
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Less
No contributions.
Low contributions.
Medium-low contributions.
Medium-high contributions.
High contributions.
More

Contribution activity

March 2025

TimRudy has no activity yet for this period.
Loading