Practice on cifar100(ResNet, DenseNet, VGG, GoogleNet, InceptionV3, InceptionV4, Inception-ResNetv2, Xception, Resnet In Resnet, ResNext,ShuffleNet, ShuffleNetv2, MobileNet, MobileNetv2, SqueezeNet…

Berkeley's Spatial Array Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Rocket Chip Generator

Everything you need to build my OpenTemp project! OpenTemp is a high accuracy thermal imager and infrared thermometer built around an STM32 and MLX90640.

Mamba SSM architecture

The First Frame-Event Long-Term Single Object Tracking Benchmark

SystemVerilog Tutorial

SpikingJelly is an open-source deep learning framework for Spiking Neural Network (SNN) based on PyTorch.

MindsDB is a Server for Artificial Intelligence Logic. Enabling developers to ship AI powered projects to production in a fast and scalable way.

Library of deep learning models and datasets designed to make deep learning more accessible and accelerate ML research.

A FPGA friendly 32 bit RISC-V CPU implementation

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RTL, Cmodel, and testbench for NVDLA

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

NVDLA SW

Documentation for NVDLA.

ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.