Refact(PA/control/ctrl): added all control signal for 46 instructions.

Fix(PA/datapath/dm): the order for big endian. Update README.md
Triple-Z · Jun 21, 2017 · 5e96a98 · 5e96a98
1 parent f9dc7c3
commit 5e96a98
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Showing 3 changed files with 136 additions and 24 deletions.
diff --git a/Project_Assignment/control/ctrl.v b/Project_Assignment/control/ctrl.v
@@ -19,8 +19,10 @@ module ctrl (ins, compare, jump, regDst, aluSrcA, aluSrcB, aluCtr, regWr, memWr,
 	wire [5:0] op;
 	wire [5:0] func;
 
-	assign op	= ins[31:26];
-	assign func	= ins[5:0];
+	assign op			= ins[31:26];
+	assign func			= ins[5:0];
+	assign begz_bltz	= ins[20:16];
+	assign mf_tc0_eret	= ins[25:21];
 
 	// Operation code;
 	parameter  	R 				= 6'b000000,
@@ -69,6 +71,14 @@ module ctrl (ins, compare, jump, regDst, aluSrcA, aluSrcB, aluCtr, regWr, memWr,
 				MFLO	= 6'b010010,
 				MTLO	= 6'b010011,
 				SYSCALL	= 6'b001100;
+	// BGEZ_BLTZ
+	parameter 	BGEZ 	= 5'b00001,
+				BLTZ 	= 5'b00000;
+	// MTC0_MFC0_ERET
+	parameter 	MTC0 	= 5'b00100,
+				MFC0 	= 5'b00000,
+				ERET 	= 5'b10000;
+
 
 	always @ ( * ) begin
 		case (op)
@@ -333,6 +343,7 @@ module ctrl (ins, compare, jump, regDst, aluSrcA, aluSrcB, aluCtr, regWr, memWr,
 				memWr		<= 2'b01;
 				immExt		<= 2'b01;
 				copWr		<= 2'b00;
+				byteExt 	<= 2'b11;
 			end
 
 			LB: begin// Load byte.
@@ -365,34 +376,136 @@ module ctrl (ins, compare, jump, regDst, aluSrcA, aluSrcB, aluCtr, regWr, memWr,
 				byteExt 	<= 2'b00;
 			end
 
-			SB: begin
+			SB: begin// Store byte.
 				aluCtr 		<= 4'b0000;
 				compare		<= 1'b0;
 				jump		<= 1'b0;
-				regDst		<= 2'b01;
+				regDst		<= 2'b00;
 				aluSrcA		<= 2'b00;
 				aluSrcB		<= 2'b01;
+				regWr		<= 2'b00;
+				memWr		<= 2'b01;
+				immExt		<= 2'b01;
+				copWr		<= 2'b00;
+				byteExt 	<= 2'b10;
+			end
+
+			BEQ: begin// Branch on equal;
+				compare		<= 1'b1;
+				jump		<= 1'b0;
+				aluSrcA		<= 2'b00;
+				aluSrcB		<= 2'b00;
+				regWr		<= 2'b00;
+				memWr		<= 2'b00;
+				copWr		<= 2'b00;
+			end
+
+			BNE: begin// Branch not on equal;
+				compare		<= 1'b1;
+				jump		<= 1'b0;
+				aluSrcA		<= 2'b00;
+				aluSrcB		<= 2'b00;
+				regWr		<= 2'b00;
+				memWr		<= 2'b00;
+				copWr		<= 2'b00;
+			end
+
+			BGTZ: begin// Branch bigger than zero;
+				compare		<= 1'b1;
+				jump		<= 1'b0;
+				aluSrcA		<= 2'b00;
+				aluSrcB		<= 2'b00;
+				regWr		<= 2'b00;
+				memWr		<= 2'b00;
+				copWr		<= 2'b00;
+			end
+
+			BLEZ: begin// Branch less or equal than zero;
+				compare		<= 1'b1;
+				jump		<= 1'b0;
+				aluSrcA		<= 2'b00;
+				aluSrcB		<= 2'b00;
+				regWr		<= 2'b00;
+				memWr		<= 2'b00;
+				copWr		<= 2'b00;
+			end
+
+			BGEZ_BLTZ: begin
+				case (begz_bltz)
+					BGEZ: begin// Branch bigger or equal than zero.
+						compare		<= 1'b1;
+						jump		<= 1'b0;
+						aluSrcA		<= 2'b00;
+						aluSrcB		<= 2'b00;
+						regWr		<= 2'b00;
+						memWr		<= 2'b00;
+						copWr		<= 2'b00;
+					end
+					BLTZ: begin// Branch less than zero.
+						compare		<= 1'b1;
+						jump		<= 1'b0;
+						aluSrcA		<= 2'b00;
+						aluSrcB		<= 2'b00;
+						regWr		<= 2'b00;
+						memWr		<= 2'b00;
+						copWr		<= 2'b00;
+					end
+				endcase
+			end
+
+			J: begin// Jump.
+				compare	<= 1'b0;
+				jump	<= 1'b1;
+				regWr	<= 2'b00;
+				memWr	<= 2'b00;
+				copWr	<= 2'b00;
+			end
+
+			JAL: begin// Jump and link.
+				compare		<= 1'b0;
+				jump		<= 1'b1;
+				regDst 		<= 2'b10;
 				memtoReg	<= 2'b00;
 				regWr		<= 2'b01;
 				memWr		<= 2'b00;
 				immExt		<= 2'b00;
 				copWr		<= 2'b00;
 			end
 
-			BEQ: begin// Branch on equal;
-			end
+			MTC0_MFC0_ERET: begin
+				case (mf_tc0_eret)
+					MTC0: begin// Move to Coprocessor 0.
+						compare 	<= 1'b0;
+						jump		<= 1'b0;
+						regDst 		<= 2'b00;
+						aluSrcB 	<= 2'b00;
+						memtoReg 	<= 2'b00;
+						regWr 		<= 2'b00;
+						memWr		<= 2'b00;
+						copWr		<= 2'b01;
+					end
 
-			BNE:
-			BGTZ:
-			BLEZ:
-			BGEZ_BLTZ:
+					MFC0: begin// Move from Coprocessor 0.
+						compare 	<= 1'b0;
+						jump		<= 1'b0;
+						regDst 		<= 2'b00;
+						memtoReg 	<= 2'b10;
+						regWr 		<= 2'b01;
+						memWr		<= 2'b00;
+						copWr		<= 2'b00;
+					end
 
-			J: begin// J-Type Instructions;
+					ERET:begin// Exception return.
+						compare 	<= 1'b0;
+						jump 		<= 1'b0;
+						memtoReg 	<= 2'b00;
+						regWr 		<= 2'b00;
+						memWr 		<= 2'b00;
+						copWr 		<= 2'b01;
+					end
+				endcase
 			end
 
-			JAL:
-			MTC0_MFC0_ERET:
-
 		endcase
 	end
 

diff --git a/Project_Assignment/datapath/dm.v b/Project_Assignment/datapath/dm.v
@@ -1,4 +1,5 @@
 `include "ext.v"
+`define BigEndianCPU 1
 
 module dm_4k (addr, din, byteExt, wEn, clk, dout);
 	input 		[11:0] 	addr;
@@ -46,10 +47,10 @@ module dm_4k (addr, din, byteExt, wEn, clk, dout);
 			if (byteExt == 2'b10) begin// Store byte.
 				tmpReg = dm[gpAddr][31:0];
 				case (byteSel)
-					2'b00: tmpReg[7:0] 		= din[7:0];
-					2'b01: tmpReg[15:8] 	= din[7:0];
-					2'b10: tmpReg[23:16] 	= din[7:0];
-					2'b11: tmpReg[31:24] 	= din[7:0];
+					2'b11: tmpReg[7:0] 		= din[7:0];
+					2'b10: tmpReg[15:8] 	= din[7:0];
+					2'b01: tmpReg[23:16] 	= din[7:0];
+					2'b00: tmpReg[31:24] 	= din[7:0];
 				endcase
 				dm[gpAddr][31:0] = tmpReg[31:0];
 			end else begin// Store word.

diff --git a/README.md b/README.md
@@ -42,8 +42,8 @@
 |`untested`	| lb 		|100000	|x		|0000	|0		|0		|01		|01			|00			|01			|01		|00		|01		|00		|01			|
 |`untested`	| lbu 		|100100	|x		|0000	|0		|0		|01		|01			|00			|01			|01		|00		|01		|00		|00			|
 |`untested`	| sb 		|101000	|x		|0000	|0		|0		|00		|01			|00			|x			|00		|01		|01		|00		|10			|
-|`untested`	| beq 		|000100	|x		|0001	|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
-|`untested`	| bne 		|000101	|x		|0001	|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
+|`untested`	| beq 		|000100	|x		|x		|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
+|`untested`	| bne 		|000101	|x		|x		|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
 |`untested`	| bgez 		|000001	|x		|x		|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
 |`untested`	| bgtz 		|000111	|x		|x		|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
 |`untested`	| blez 		|000110	|x		|x		|1		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
@@ -53,9 +53,7 @@
 |`untested`	| jalr 		|000000	|001001	|x		|0		|1		|01		|x			|x			|00			|01		|00		|x		|00		|x			|
 |`untested`	| jal 		|000011	|x		|x		|0		|1		|10		|x			|x			|00			|01		|00		|00		|00		|x			|
 
-
-
-|Status		|Ins Type	|op 	|func	|ALUctr	|Compare|Jump	|RegDst	|ALUSrcB	|ALUSrcA	|MemtoReg	|RegWr	|MemWr	|ExtOp	|CopWr	|ByteExt	|
+|Status		|Ins Type	|op 	|func	|ALUctr	|Compare|Jump	|RegDst	|ALUSrcB	|ALUSrcA	|MemtoReg	|RegWr	|MemWr	|ImmExt	|CopWr	|ByteExt	|
 |:----:		|:-------:	|:----:	|:----:	|:----:	|:----:	|:----:	|:----:	|:-------:	|:------:	|:------:	|:----:	|:----:	|:----:	|:----:	|:------:	|
 |`untested`	| mult 		|000000	|011000	|1001	|0		|0		|x		|00			|00			|x			|00		|00		|x		|00		|x			|
 |`untested`	| mfhi 		|000000	|010000	|1101	|0		|0		|01		|00			|00			|00			|01		|00		|x		|00		|x			|
@@ -83,7 +81,7 @@
 
 ### Control Module
 
-- [ ] [CTRL (Controller)](Project_Assignment/control/ctrl.v)
+- [x] [CTRL (Controller)](Project_Assignment/control/ctrl.v)
 
 ### Creator Module