On board experiment on 6/9/2017.

Triple-Z · Jun 9, 2017 · 8a581de · 8a581de
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diff --git a/Project_2_OC/TestProject/TestProject.gise b/Project_2_OC/TestProject/TestProject.gise
diff --git a/Project_2_OC/TestProject/TestProject.xise b/Project_2_OC/TestProject/TestProject.xise
diff --git a/Project_2_OC/TestProject/_ngo/netlist.lst b/Project_2_OC/TestProject/_ngo/netlist.lst
@@ -0,0 +1,4 @@
+F:\Verilog\Project_2_OC\TestProject\adder_display.ngc 1497010035
+F:\Verilog\Project_2_OC\TestProject/lcd_module.ngc 1462996372
+F:\Verilog\Project_2_OC\TestProject/lcd_rom.ngc 1462996372
+OK
diff --git a/Project_2_OC/TestProject/_xmsgs/bitgen.xmsgs b/Project_2_OC/TestProject/_xmsgs/bitgen.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/Project_2_OC/TestProject/_xmsgs/map.xmsgs b/Project_2_OC/TestProject/_xmsgs/map.xmsgs
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N35</arg> has no load.
+</msg>
+
+<msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">2</arg> more times for the following (max. 5 shown):
+<arg fmt="%s" index="3">N36,
+lcd_module/touch_module/int_io/O</arg>
+To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
+</msg>
+
+<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
+</msg>
+
+<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
+</msg>
+
+<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
+</msg>
+
+<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
+</msg>
+
+<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
+</msg>
+
+<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
+</msg>
+
+</messages>
+
diff --git a/Project_2_OC/TestProject/_xmsgs/ngdbuild.xmsgs b/Project_2_OC/TestProject/_xmsgs/ngdbuild.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N35</arg>&apos; has no driver
+</msg>
+
+<msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N36</arg>&apos; has no driver
+</msg>
+
+</messages>
+
diff --git a/Project_2_OC/TestProject/_xmsgs/par.xmsgs b/Project_2_OC/TestProject/_xmsgs/par.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/Project_2_OC/TestProject/_xmsgs/pn_parser.xmsgs b/Project_2_OC/TestProject/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;F:/Verilog/Project_2_OC/TestProject/adder.v\&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;F:/Verilog/Project_2_OC/TestProject/adder_display.v\&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;F:/Verilog/Project_2_OC/TestProject/lcd_module.v\&quot; into library work</arg>
+</msg>
+
+<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;F:/Verilog/Project_2_OC/TestProject/testbench.v\&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/Project_2_OC/TestProject/_xmsgs/trce.xmsgs b/Project_2_OC/TestProject/_xmsgs/trce.xmsgs
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+
+<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+
+</messages>
+
diff --git a/Project_2_OC/TestProject/_xmsgs/xst.xmsgs b/Project_2_OC/TestProject/_xmsgs/xst.xmsgs
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="Xst" num="3231" delta="new" >The small RAM &lt;<arg fmt="%s" index="1">Mram__n0043</arg>&gt; will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
+</msg>
+
+<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch &lt;<arg fmt="%s" index="1">display_name_7</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_13</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_15</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_19</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_21</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_23</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_25</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_27</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_34</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_35</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_37</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">display_name_39</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">adder_display</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">display_name_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">adder_display</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">8 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;display_name_3&gt; &lt;display_name_6&gt; &lt;display_name_16&gt; &lt;display_name_17&gt; &lt;display_name_20&gt; &lt;display_name_24&gt; &lt;display_name_33&gt; &lt;display_name_36&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">display_name_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">adder_display</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;display_name_5&gt; &lt;display_name_9&gt; &lt;display_name_11&gt; &lt;display_name_18&gt; &lt;display_name_32&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">display_name_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">adder_display</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;display_name_10&gt; &lt;display_name_12&gt; &lt;display_name_14&gt; &lt;display_name_22&gt; &lt;display_name_26&gt; &lt;display_name_30&gt; &lt;display_name_38&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">display_valid</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">adder_display</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;display_name_8&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">lcd_init_module/display_x_l_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">lcd_module</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;lcd_init_module/display_x_l_2_1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">lcd_init_module/display_y_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">lcd_module</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;lcd_init_module/display_y_1_1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">lcd_init_module/display_y_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">lcd_module</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;lcd_init_module/display_y_3_1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">lcd_init_module/display_x_l_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">lcd_module</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;lcd_init_module/display_x_l_2_1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">lcd_init_module/display_y_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">lcd_module</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;lcd_init_module/display_y_1_1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">lcd_init_module/display_y_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">lcd_module</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;lcd_init_module/display_y_3_1&gt; </arg>
+</msg>
+
+<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+
+</messages>
+
diff --git a/Project_2_OC/TestProject/adder.ucf b/Project_2_OC/TestProject/adder.ucf
@@ -0,0 +1,48 @@
+############################################################################
+# VCC AUX VOLTAGE 
+############################################################################
+CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
+
+#ʱ���ź�����
+NET "clk" LOC = J1 | IOSTANDARD = "LVTTL";
+NET "clk" TNM_NET = clk;
+TIMESPEC TS_clk = PERIOD "clk" 100 ns HIGH 50%;
+NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#���忪�أ�����������Ϊ��λ�ź�,�͵�ƽ��Ч
+NET "resetn" LOC = U3 | IOSTANDARD = "LVTTL";
+
+#led�����ӣ��������
+NET "led_cout" LOC = A8  | IOSTANDARD = "LVTTL";  #led3 
+
+#���뿪�����ӣ���������
+NET "input_sel" LOC = T2 | IOSTANDARD = "LVTTL";  #sw0 
+NET "sw_cin"    LOC = M2 | IOSTANDARD = "LVTTL";  #sw6
+
+#�������������ӣ�����Ҫ����
+NET "lcd_rst" LOC = D14 | IOSTANDARD = "LVTTL";
+NET "lcd_cs"  LOC = D12 | IOSTANDARD = "LVTTL";
+NET "lcd_rs"  LOC = E12 | IOSTANDARD = "LVTTL";
+NET "lcd_wr"  LOC = D13 | IOSTANDARD = "LVTTL";
+NET "lcd_rd"  LOC = F13 | IOSTANDARD = "LVTTL";
+NET "lcd_bl_ctr" LOC = A15 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[0]"   LOC = C13 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[1]"   LOC = E14 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[2]"   LOC = C14 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[3]"   LOC = D15 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[4]"   LOC = C15 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[5]"   LOC = F14 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[6]"   LOC = C16 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[7]"   LOC = D17 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[8]"   LOC = E16 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[9]"   LOC = B12 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[10]"  LOC = F15 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[11]"  LOC = C12 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[12]"  LOC = A12 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[13]"  LOC = A14 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[14]"  LOC = A13 | IOSTANDARD = "LVTTL";
+NET "lcd_data_io[15]"  LOC = B14 | IOSTANDARD = "LVTTL";
+NET "ct_int" LOC = A18 | IOSTANDARD = "LVTTL";
+NET "ct_sda" LOC = A16 | IOSTANDARD = "LVTTL";
+NET "ct_scl" LOC = B18 | IOSTANDARD = "LVTTL";
+NET "ct_rstn"LOC = C17 | IOSTANDARD = "LVTTL";
diff --git a/Project_2_OC/TestProject/adder.v b/Project_2_OC/TestProject/adder.v
@@ -0,0 +1,17 @@
+`timescale 1ns / 1ps
+//*************************************************************************
+//   > 文件名: adder.v
+//   > 描述  ：加法器，直接使用"+"，会自动调用库里的加法器
+//   > 作者  : LOONGSON
+//   > 日期  : 2016-04-14
+//*************************************************************************
+module adder(
+    input  [31:0] operand1,
+    input  [31:0] operand2,
+    input         cin,
+    output [31:0] result,
+    output        cout
+    );
+    assign {cout,result} = operand1 + operand2 + cin;
+
+endmodule