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Commits on Jan 10, 2024

• tty: Add SBI debug console support to HVC SBI driver

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Commits on Feb 7, 2023

• RISC-V: KVM: Increment firmware pmu events

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• RISC-V: KVM: Support firmware events

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• RISC-V: KVM: Implement perf support without sampling

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• RISC-V: KVM: Implement trap & emulate for hpmcounters

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• RISC-V: KVM: Disable all hpmcounter access for VS/VU mode

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• RISC-V: KVM: Make PMU functionality depend on Sscofpmf

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• RISC-V: KVM: Add SBI PMU extension support

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• RISC-V: KVM: Add skeleton support for perf

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• RISC-V: KVM: Modify SBI extension handler to return SBI error code

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• RISC-V: KVM: Return correct code for hsm stop function

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• RISC-V: KVM: Define a probe function for SBI extension data structures

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• RISC-V: Improve SBI PMU extension related definitions

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• perf: RISC-V: Improve privilege mode filtering for perf

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• perf: RISC-V: Define helper functions expose hpm counter width and count

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Commits on Aug 12, 2022

• RISC-V: KVM: Support sstc extension

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Commits on Aug 11, 2022

• RISC-V: Improve SBI definitions

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• RISC-V: Move counter info definition to sbi header file

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• RISC-V: Fix SBI PMU calls for RV32

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• RISC-V: Update user page mapping only once during start

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• RISC-V: Fix counter restart during overflow for RV32

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• RISC-V: Prefer sstc extension if available

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• RISC-V: Enable sstc extension parsing from DT

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• RISC-V: Add SSTC extension CSR details

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Commits on Jul 29, 2022

• RISC-V: KVM: Improve ISA extension by using a bitmap

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Commits on May 20, 2022

• RISC-V: KVM: Introduce ISA extension register

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Commits on Apr 20, 2022

• RISC-V: KVM: Restrict the extensions that can be disabled

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• RISC-V: KVM: Remove 's' & 'u' as valid ISA extension

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Commits on Mar 31, 2022

• RISC-V: Declare per cpu boot data as static

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• RISC-V: Fix a comment typo in riscv_of_parent_hartid()

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Commits on Mar 21, 2022

• MAINTAINERS: Add entry for RISC-V PMU drivers

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• Documentation: riscv: Remove the old documentation

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• RISC-V: Add sscofpmf extension support

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• RISC-V: Add perf platform driver based on SBI PMU extension

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• RISC-V: Add RISC-V SBI PMU extension definitions

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